Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	340434	1		T1	2		T2	2		T3	2
all_values[1]	340434	1		T1	2		T2	2		T3	2
all_values[2]	340434	1		T1	2		T2	2		T3	2
all_values[3]	340434	1		T1	2		T2	2		T3	2
all_values[4]	340434	1		T1	2		T2	2		T3	2
all_values[5]	340434	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	687121	1		T1	12		T2	12		T3	12
auto[1]	1355483	1		T6	8024		T22	7248		T23	5488

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	999903	1		T1	7		T2	7		T3	7
auto[1]	1042701	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	340288	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	146	1		T259	2		T260	1		T261	7
all_values[1]	auto[0]	auto[1]	340278	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	156	1		T259	3		T260	3		T261	3
all_values[2]	auto[0]	auto[0]	1589	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	55	1		T261	5		T312	1		T313	2
all_values[2]	auto[1]	auto[0]	338726	1		T6	2006		T22	1812		T23	1372
all_values[2]	auto[1]	auto[1]	64	1		T259	2		T260	3		T313	1
all_values[3]	auto[0]	auto[0]	1588	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	52	1		T261	1		T312	1		T313	2
all_values[3]	auto[1]	auto[0]	74086	1		T6	1003		T22	906		T23	686
all_values[3]	auto[1]	auto[1]	264708	1		T6	1003		T22	906		T23	686
all_values[4]	auto[0]	auto[0]	1137	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	507	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	242556	1		T6	1003		T22	906		T23	686
all_values[4]	auto[1]	auto[1]	96234	1		T6	1003		T22	906		T23	686
all_values[5]	auto[0]	auto[0]	1488	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	139	1		T17	1		T32	1		T33	1
all_values[5]	auto[1]	auto[0]	338733	1		T6	2006		T22	1812		T23	1372
all_values[5]	auto[1]	auto[1]	74	1		T259	1		T260	1		T261	4