---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.PrimRspPayLoad_A	0	0	380986542	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	380986542	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	380986542	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	380986542	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	380986542	0	0	0
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	380986542	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	380986542	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	380986542	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	380986542	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	380986542	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	380986542	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1060	1060	0	0
tb.dut.FlashAddrKnown_A	0	0	380986542	297811680	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.FlashKnownO_A	0	0	380986542	380077602	0	0
tb.dut.FlashProgKnown_A	0	0	380986542	182557780	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	380986542	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	380986542	50	0	0
tb.dut.IntrErrO_A	0	0	380986542	380077602	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	380986542	380077602	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	380986542	380077602	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	380986542	380077602	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	380986542	380077602	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	380986542	380077602	0	0
tb.dut.MemRspPayLoad_A	0	0	380986542	5909780	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	380986542	380077602	0	0
tb.dut.MemTlDValidKnownO_A	0	0	380986542	380077602	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	380986542	380077602	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	380986542	380077602	0	0
tb.dut.RspPayLoad_A	0	0	380781014	33789565	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.TdoEnIsOne_A	0	0	380986542	380077602	0	0
tb.dut.TdoKnown_A	0	0	380986542	380077602	0	0
tb.dut.TlAReadyKnownO_A	0	0	380986542	380077602	0	0
tb.dut.TlDValidKnownO_A	0	0	380986542	380077602	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	383421541	4328	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	383421541	2027	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	383421541	3472	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	383421541	3077	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	383421541	3366	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	383421541	3236	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	383421541	3154	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	383421541	3358	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	383421541	2973	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	383421541	3346	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	383421541	3439	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	383421541	2710	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	383421541	1826	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	383421541	1301	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	383421541	1844	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	383421541	1932	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	383421541	1959	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	383421541	1994	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	383421541	1955	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	383421541	1819	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	383421541	2053	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	383421541	1861	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	383421541	3245	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	383421541	1641	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	383421541	3464	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	383421541	2696	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	383421541	1963	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	383421541	2069	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	383421541	3488	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	383421541	3437	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	383421541	2816	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	383421541	3105	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	383421541	3575	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	383421541	3087	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	383421541	3111	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	383421541	2941	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	383421541	2740	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	383421541	3450	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	383421541	2044	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	383421541	1338	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	383421541	2004	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	383421541	1784	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	383421541	1937	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	383421541	1413	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	383421541	2007	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	383421541	1385	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	383421541	1925	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	383421541	1995	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	383421541	3040	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	383421541	1842	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	383421541	3249	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	383421541	3372	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	383421541	1803	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	383421541	1432	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	383421541	2162	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	383421541	3009	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	383421541	1785	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	383421541	2153	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	383421541	2039	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	383421541	1592	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	383421541	2812	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	383421541	2050	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	383421541	2195	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	383421541	2142	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	383421541	2124	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	383421541	2061	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	383421541	1666	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	383421541	2124	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	383421541	2184	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	383421541	3213	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	383421541	3428	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	383421541	3705	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	383421541	3292	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	383421541	3342	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	383421541	3377	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	383421541	2953	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	383421541	3371	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	383421541	744	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	383421541	1928	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	383421541	1460	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	383421541	1853	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	383421541	1855	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	383421541	2003	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	383421541	1533	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	383421541	1866	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	383421541	2022	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	383421541	1489	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	380986542	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	380986542	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	380986542	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	380986542	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	380986542	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	380986542	31	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	383421466	30915129	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	383421466	382426979	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	383421466	34646851	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	383421466	382426979	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
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tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1270	1270	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	383422170	4681184	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	383421466	6958	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	383422170	28323393	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	383216642	28622036	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	383421466	5275	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	383422170	30915139	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	383422170	34646867	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	383422170	30915139	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	383422170	34646867	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	383422170	34646867	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	383422170	34646867	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	383421466	5331	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	383421466	6278	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1275	1275	0	0
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_ctrl_arb.u_state_regs_A	0	0	380986617	380077677	0	0
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_disable_buf.OutputsKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A	0	0	380986542	2158936	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A	0	0	380986542	2158936	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A	0	0	380986542	23135694	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	380986542	1217041	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	380986542	17775	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	380986542	8087	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	380986542	119592573	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	380986542	119592573	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	380986542	119592573	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	380986542	46245943	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	380986542	125751195	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	380986542	119592573	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	380986542	119592573	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	380986542	125751195	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	380986542	119340069	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	380986542	119340069	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	380986542	119340069	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	380986542	46245945	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	380986542	125498689	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	380986542	119340069	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	380986542	119340069	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	380986542	125498689	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A	0	0	380986542	828040	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A	0	0	380986542	2125790	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A	0	0	380986542	53250090	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	380986542	723261	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	380986542	723258	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	380986542	723200	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	380986542	723198	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	380986542	722849	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	380986542	722848	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	380986542	722439	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	380986542	722436	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	380986542	12978497	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	12978497	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	380986542	3719780	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	380986542	3719791	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	380986543	8897301	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	380781014	14002619	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380781014	14002619	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	380781014	53242235	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380781014	53242235	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	380986542	2846076	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	380986542	2846076	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	380986542	2846076	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	380986542	276641788	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	380986542	2846076	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	380986542	2846076	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	380986542	98164309	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	380986542	31491	0	1054
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A	0	0	380781014	2802451	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380781014	2802451	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A	0	0	380986542	2219825	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A	0	0	380986542	2219825	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A	0	0	380986542	22778757	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	380986542	1173909	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	380986542	11747	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	380986542	6058	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	380986542	43102648	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	380986542	107726263	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	380986542	107726263	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	380986542	43102648	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	380986542	107726263	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	380986542	101649443	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	380986542	107726263	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A	0	0	380986542	649548	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A	0	0	380986542	1831222	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A	0	0	380986542	50057009	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	380986542	679654	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	380986542	679651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	380986542	679479	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	380986542	679478	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	380986542	679278	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	380986542	679278	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	380986542	678898	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	380986542	678895	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	380986542	11271073	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	11271073	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	380986542	3366850	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	380986542	3366858	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	380986543	7878489	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	380781014	12617580	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380781014	12617580	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	380781014	50048814	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380781014	50048814	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	380986542	2710373	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	380986542	2710373	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	380986542	2710373	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	380986542	289862192	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	380986542	2710373	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	380986542	2710373	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	380986542	85667225	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	380986542	19554	0	1054
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A	0	0	380781014	3167090	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A	0	0	380781014	379872074	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380781014	3167090	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A	0	0	380986542	34413900	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	34413900	0	0
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	18827993	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	2843648	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	3662484	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	380986542	104774409	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	104774409	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	66488734	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	7578761	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	6513758	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	6548044	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	380986542	86667248	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	86667248	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	380986542	66663441	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit	0	0	383421466	57998	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv	0	0	383421466	57998	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse	0	0	383421466	38628	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1275	1275	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse	0	0	383421466	19370	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A	0	0	375026740	374117800	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	375026740	374082244	0	2772
tb.dut.u_flash_hw_if.DisableChk_A	0	0	368978349	5599715	0	44
tb.dut.u_flash_hw_if.ProgRdVerify_A	0	0	367032600	2043535	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq	0	0	380986617	10111	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq	0	0	380894705	9780	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq	0	0	380986617	10072	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq	0	0	366073038	9773	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs_A	0	0	380986617	380077677	0	0
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_flash_hw_if.u_state_regs_A	0	0	380986617	380077677	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	375026815	374117875	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_flash_mp.BankEraseData_A	0	0	380986617	7669117	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	380986617	9306779	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	380986617	264485613	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	380986617	297923664	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	380986617	33438051	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	375492474	111880	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	380986617	16975896	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	380986617	155035153	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	380986617	297811745	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	380986617	297811745	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	1060	1060	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	1060	1060	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	1060	1060	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	1060	1060	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	1060	1060	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	1060	1060	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	375001785	374092845	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	375001785	374057424	0	2622
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	375026815	374117875	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_prog_fifo.DataKnown_A	0	0	380986542	188892125	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	188892125	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	375026740	374117800	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	375026740	374117800	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	380986542	380077602	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1060	1060	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1060	1060	0	0
tb.dut.u_reg_core.en2addrHit	0	0	383421541	24205444	0	0
tb.dut.u_reg_core.reAfterRv	0	0	383421541	24205421	0	0
tb.dut.u_reg_core.rePulse	0	0	383421541	21841267	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	383421541	382427054	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	383421541	382427054	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	383421466	30915129	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	383421466	34646851	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	383421466	2198282	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	383421466	2512731	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	383421466	4003209	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	383421466	3857066	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	383421466	24643050	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	383421466	28277054	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	383421466	382426979	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1275	1275	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1275	1275	0	0
tb.dut.u_reg_core.wePulse	0	0	383421541	2364154	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	380986617	380077677	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	375026815	374117875	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	375026815	374117875	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	375026815	374117875	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	375026815	374117875	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	380986542	48917089	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	48917089	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_A	0	0	380986542	5909651	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	380986542	4459944	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	380986542	4459944	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	380986542	35863449	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	35863449	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1060	1060	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	380986542	5904423	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	5904423	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	380986542	34413900	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	34413900	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1060	1060	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	375026740	374117800	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	375026740	374117800	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1060	1060	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	380986542	380077602	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1060	1060	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.TlOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A	0	0	380986542	2483778	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	380986542	2483778	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	2483778	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1060	1060	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1060	1060	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1060	1060	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1060	1060	0	0
tb.dut.u_to_rd_fifo.TlOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A	0	0	380986542	3853157	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1060	1060	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	380986542	3156051	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	380322610	3150062	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1060	1060	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	380986542	3853157	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	3853157	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1060	1060	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1060	1060	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	380781014	3846162	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	3862422	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	380986542	3156051	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	380986542	380077602	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	380986542	3156051	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	380986542	31491	0	1054
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	380986542	19554	0	1054
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	375026740	374082244	0	2772
tb.dut.u_flash_hw_if.DisableChk_A	0	0	368978349	5599715	0	44
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	375001785	374057424	0	2622
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	375026815	374082304	0	2772

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	383422170	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	383422170	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	383422170	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	383422170	104454	104454	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	383422170	11	11	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	383422170	6	6	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	383422170	5	5	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	383422170	15970	15970	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	383422170	319349	319349	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	383422170	16078485	16078485	1249

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	383422170	104454	104454	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	383422170	11	11	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	383422170	6	6	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	383422170	5	5	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	383422170	15970	15970	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	383422170	319349	319349	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	383422170	16078485	16078485	1249