Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9217 |
1 |
|
T1 |
2 |
|
T2 |
27 |
|
T16 |
1 |
| others[1] |
1037 |
1 |
|
T1 |
6 |
|
T2 |
18 |
|
T6 |
1 |
| others[2] |
1065 |
1 |
|
T1 |
2 |
|
T2 |
16 |
|
T3 |
1 |
| others[3] |
1716 |
1 |
|
T1 |
3 |
|
T2 |
29 |
|
T4 |
1 |
| false |
579 |
1 |
|
T2 |
11 |
|
T57 |
1 |
|
T94 |
6 |
| true |
1358 |
1 |
|
T10 |
1 |
|
T121 |
1 |
|
T79 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T2 |
12 |
|
T27 |
1 |
|
T368 |
1 |
| others[1] |
196 |
1 |
|
T2 |
11 |
|
T378 |
1 |
|
T368 |
1 |
| others[2] |
233 |
1 |
|
T2 |
10 |
|
T25 |
1 |
|
T33 |
1 |
| others[3] |
375 |
1 |
|
T2 |
20 |
|
T57 |
1 |
|
T192 |
1 |
| false |
123 |
1 |
|
T2 |
6 |
|
T6 |
1 |
|
T20 |
1 |
| true |
13824 |
1 |
|
T1 |
13 |
|
T2 |
42 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T2 |
10 |
|
T386 |
1 |
|
T383 |
1 |
| others[1] |
199 |
1 |
|
T2 |
9 |
|
T17 |
1 |
|
T33 |
1 |
| others[2] |
214 |
1 |
|
T2 |
8 |
|
T177 |
1 |
|
T382 |
1 |
| others[3] |
319 |
1 |
|
T2 |
11 |
|
T96 |
1 |
|
T28 |
1 |
| false |
108 |
1 |
|
T2 |
4 |
|
T26 |
1 |
|
T89 |
1 |
| true |
13896 |
1 |
|
T1 |
13 |
|
T2 |
59 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9389 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T16 |
1 |
| others[1] |
1160 |
1 |
|
T1 |
4 |
|
T2 |
16 |
|
T4 |
1 |
| others[2] |
1198 |
1 |
|
T1 |
4 |
|
T2 |
24 |
|
T10 |
1 |
| others[3] |
2101 |
1 |
|
T1 |
2 |
|
T2 |
28 |
|
T22 |
1 |
| false |
697 |
1 |
|
T2 |
12 |
|
T3 |
1 |
|
T17 |
1 |
| true |
427 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9395 |
1 |
|
T1 |
5 |
|
T2 |
15 |
|
T4 |
1 |
| others[1] |
1247 |
1 |
|
T1 |
3 |
|
T2 |
15 |
|
T36 |
1 |
| others[2] |
1292 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T3 |
1 |
| others[3] |
1944 |
1 |
|
T1 |
2 |
|
T2 |
45 |
|
T16 |
1 |
| false |
667 |
1 |
|
T1 |
2 |
|
T2 |
9 |
|
T6 |
1 |
| true |
427 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T2 |
5 |
|
T96 |
2 |
|
T366 |
1 |
| others[1] |
95 |
1 |
|
T2 |
3 |
|
T177 |
1 |
|
T379 |
1 |
| others[2] |
113 |
1 |
|
T2 |
7 |
|
T38 |
1 |
|
T370 |
1 |
| others[3] |
189 |
1 |
|
T2 |
5 |
|
T368 |
2 |
|
T372 |
1 |
| false |
48 |
1 |
|
T2 |
4 |
|
T37 |
1 |
|
T366 |
1 |
| true |
14438 |
1 |
|
T1 |
13 |
|
T2 |
77 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T2 |
8 |
|
T96 |
1 |
|
T113 |
1 |
| others[1] |
198 |
1 |
|
T2 |
9 |
|
T6 |
1 |
|
T369 |
1 |
| others[2] |
208 |
1 |
|
T2 |
11 |
|
T59 |
1 |
|
T24 |
1 |
| others[3] |
403 |
1 |
|
T2 |
19 |
|
T89 |
1 |
|
T81 |
1 |
| false |
117 |
1 |
|
T2 |
6 |
|
T20 |
1 |
|
T60 |
1 |
| true |
13832 |
1 |
|
T1 |
13 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9196 |
1 |
|
T1 |
5 |
|
T2 |
22 |
|
T79 |
1 |
| others[1] |
1068 |
1 |
|
T1 |
2 |
|
T2 |
15 |
|
T94 |
7 |
| others[2] |
1006 |
1 |
|
T1 |
1 |
|
T2 |
18 |
|
T3 |
1 |
| others[3] |
1730 |
1 |
|
T1 |
4 |
|
T2 |
33 |
|
T6 |
1 |
| false |
553 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T19 |
1 |
| true |
1419 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T2 |
10 |
|
T37 |
1 |
|
T89 |
1 |
| others[1] |
192 |
1 |
|
T2 |
7 |
|
T303 |
1 |
|
T368 |
1 |
| others[2] |
227 |
1 |
|
T2 |
11 |
|
T20 |
1 |
|
T325 |
2 |
| others[3] |
406 |
1 |
|
T2 |
21 |
|
T6 |
1 |
|
T17 |
1 |
| false |
114 |
1 |
|
T2 |
6 |
|
T325 |
1 |
|
T82 |
9 |
| true |
13809 |
1 |
|
T1 |
13 |
|
T2 |
46 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
195 |
1 |
|
T2 |
10 |
|
T28 |
1 |
|
T367 |
1 |
| others[1] |
206 |
1 |
|
T2 |
11 |
|
T37 |
1 |
|
T367 |
1 |
| others[2] |
216 |
1 |
|
T2 |
12 |
|
T32 |
1 |
|
T27 |
1 |
| others[3] |
392 |
1 |
|
T2 |
21 |
|
T96 |
1 |
|
T38 |
1 |
| false |
111 |
1 |
|
T2 |
6 |
|
T383 |
1 |
|
T387 |
1 |
| true |
13852 |
1 |
|
T1 |
13 |
|
T2 |
41 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9369 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T51 |
138 |
| others[1] |
1217 |
1 |
|
T1 |
3 |
|
T2 |
22 |
|
T16 |
1 |
| others[2] |
1278 |
1 |
|
T1 |
5 |
|
T2 |
19 |
|
T3 |
1 |
| others[3] |
2026 |
1 |
|
T1 |
3 |
|
T2 |
35 |
|
T22 |
1 |
| false |
652 |
1 |
|
T2 |
7 |
|
T94 |
10 |
|
T180 |
7 |
| true |
430 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1301 |
1 |
|
T1 |
1 |
|
T2 |
28 |
|
T4 |
1 |
| others[1] |
1206 |
1 |
|
T1 |
1 |
|
T2 |
19 |
|
T94 |
22 |
| others[2] |
1232 |
1 |
|
T1 |
5 |
|
T2 |
15 |
|
T19 |
1 |
| others[3] |
2035 |
1 |
|
T1 |
4 |
|
T2 |
25 |
|
T3 |
1 |
| false |
624 |
1 |
|
T1 |
2 |
|
T2 |
14 |
|
T22 |
1 |
| true |
427 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T2 |
6 |
|
T369 |
1 |
|
T372 |
1 |
| others[1] |
89 |
1 |
|
T2 |
6 |
|
T177 |
1 |
|
T368 |
1 |
| others[2] |
104 |
1 |
|
T2 |
5 |
|
T366 |
1 |
|
T367 |
1 |
| others[3] |
177 |
1 |
|
T2 |
7 |
|
T96 |
2 |
|
T37 |
1 |
| false |
46 |
1 |
|
T2 |
2 |
|
T368 |
1 |
|
T366 |
1 |
| true |
6322 |
1 |
|
T1 |
13 |
|
T2 |
75 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T2 |
10 |
|
T24 |
1 |
|
T368 |
2 |
| others[1] |
220 |
1 |
|
T2 |
10 |
|
T96 |
2 |
|
T89 |
1 |
| others[2] |
189 |
1 |
|
T2 |
3 |
|
T6 |
1 |
|
T303 |
1 |
| others[3] |
379 |
1 |
|
T2 |
17 |
|
T17 |
1 |
|
T59 |
1 |
| false |
119 |
1 |
|
T2 |
6 |
|
T133 |
1 |
|
T209 |
1 |
| true |
5679 |
1 |
|
T1 |
13 |
|
T2 |
55 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1020 |
1 |
|
T1 |
4 |
|
T2 |
18 |
|
T53 |
1 |
| others[1] |
1040 |
1 |
|
T1 |
2 |
|
T2 |
24 |
|
T10 |
1 |
| others[2] |
1054 |
1 |
|
T1 |
3 |
|
T2 |
17 |
|
T94 |
12 |
| others[3] |
1778 |
1 |
|
T1 |
4 |
|
T2 |
37 |
|
T3 |
1 |
| false |
571 |
1 |
|
T2 |
5 |
|
T23 |
1 |
|
T94 |
3 |
| true |
1362 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T2 |
9 |
|
T17 |
1 |
|
T37 |
1 |
| others[1] |
220 |
1 |
|
T2 |
8 |
|
T89 |
1 |
|
T34 |
1 |
| others[2] |
228 |
1 |
|
T2 |
11 |
|
T378 |
1 |
|
T388 |
1 |
| others[3] |
348 |
1 |
|
T2 |
23 |
|
T96 |
1 |
|
T204 |
1 |
| false |
112 |
1 |
|
T2 |
2 |
|
T57 |
1 |
|
T269 |
1 |
| true |
5718 |
1 |
|
T1 |
13 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T2 |
5 |
|
T17 |
1 |
|
T96 |
1 |
| others[1] |
213 |
1 |
|
T2 |
11 |
|
T27 |
1 |
|
T28 |
1 |
| others[2] |
189 |
1 |
|
T2 |
6 |
|
T371 |
1 |
|
T389 |
1 |
| others[3] |
385 |
1 |
|
T2 |
21 |
|
T37 |
1 |
|
T177 |
1 |
| false |
90 |
1 |
|
T2 |
2 |
|
T57 |
1 |
|
T82 |
3 |
| true |
5739 |
1 |
|
T1 |
13 |
|
T2 |
56 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T1 |
2 |
|
T2 |
17 |
|
T4 |
1 |
| others[1] |
1249 |
1 |
|
T1 |
4 |
|
T2 |
28 |
|
T36 |
1 |
| others[2] |
1193 |
1 |
|
T1 |
3 |
|
T2 |
19 |
|
T94 |
15 |
| others[3] |
2058 |
1 |
|
T1 |
2 |
|
T2 |
27 |
|
T3 |
1 |
| false |
666 |
1 |
|
T1 |
2 |
|
T2 |
10 |
|
T94 |
15 |
| true |
450 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1304 |
1 |
|
T1 |
3 |
|
T2 |
20 |
|
T16 |
1 |
| others[1] |
1201 |
1 |
|
T1 |
2 |
|
T2 |
24 |
|
T3 |
1 |
| others[2] |
1210 |
1 |
|
T1 |
3 |
|
T2 |
15 |
|
T53 |
1 |
| others[3] |
2041 |
1 |
|
T1 |
4 |
|
T2 |
28 |
|
T4 |
1 |
| false |
653 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T94 |
9 |
| true |
416 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
91 |
1 |
|
T2 |
3 |
|
T57 |
1 |
|
T96 |
1 |
| others[1] |
93 |
1 |
|
T2 |
8 |
|
T369 |
1 |
|
T82 |
5 |
| others[2] |
123 |
1 |
|
T2 |
6 |
|
T37 |
1 |
|
T38 |
1 |
| others[3] |
156 |
1 |
|
T2 |
2 |
|
T27 |
1 |
|
T28 |
1 |
| false |
48 |
1 |
|
T2 |
1 |
|
T96 |
1 |
|
T177 |
1 |
| true |
6314 |
1 |
|
T1 |
13 |
|
T2 |
81 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T2 |
5 |
|
T20 |
1 |
|
T368 |
2 |
| others[1] |
232 |
1 |
|
T2 |
19 |
|
T25 |
1 |
|
T113 |
1 |
| others[2] |
199 |
1 |
|
T2 |
11 |
|
T6 |
1 |
|
T96 |
1 |
| others[3] |
381 |
1 |
|
T2 |
15 |
|
T38 |
1 |
|
T21 |
1 |
| false |
117 |
1 |
|
T2 |
6 |
|
T204 |
1 |
|
T49 |
1 |
| true |
5655 |
1 |
|
T1 |
13 |
|
T2 |
45 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
984 |
1 |
|
T1 |
1 |
|
T2 |
16 |
|
T6 |
1 |
| others[1] |
1095 |
1 |
|
T1 |
3 |
|
T2 |
19 |
|
T3 |
1 |
| others[2] |
1054 |
1 |
|
T1 |
1 |
|
T2 |
16 |
|
T4 |
1 |
| others[3] |
1751 |
1 |
|
T1 |
6 |
|
T2 |
39 |
|
T16 |
1 |
| false |
543 |
1 |
|
T1 |
2 |
|
T2 |
11 |
|
T94 |
7 |
| true |
1398 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
7 |
|
T25 |
1 |
|
T382 |
1 |
| others[1] |
194 |
1 |
|
T2 |
7 |
|
T17 |
1 |
|
T38 |
1 |
| others[2] |
214 |
1 |
|
T2 |
7 |
|
T37 |
1 |
|
T272 |
1 |
| others[3] |
385 |
1 |
|
T2 |
12 |
|
T96 |
1 |
|
T113 |
1 |
| false |
115 |
1 |
|
T2 |
3 |
|
T378 |
1 |
|
T321 |
1 |
| true |
5699 |
1 |
|
T1 |
13 |
|
T2 |
65 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T2 |
8 |
|
T96 |
1 |
|
T368 |
1 |
| others[1] |
226 |
1 |
|
T2 |
11 |
|
T32 |
1 |
|
T27 |
1 |
| others[2] |
229 |
1 |
|
T2 |
14 |
|
T49 |
1 |
|
T373 |
1 |
| others[3] |
326 |
1 |
|
T2 |
12 |
|
T38 |
1 |
|
T177 |
1 |
| false |
109 |
1 |
|
T2 |
6 |
|
T386 |
1 |
|
T82 |
4 |
| true |
5712 |
1 |
|
T1 |
13 |
|
T2 |
50 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T22 |
1 |
| others[1] |
1190 |
1 |
|
T1 |
1 |
|
T2 |
20 |
|
T4 |
1 |
| others[2] |
1231 |
1 |
|
T1 |
2 |
|
T2 |
22 |
|
T57 |
1 |
| others[3] |
2140 |
1 |
|
T1 |
7 |
|
T2 |
35 |
|
T16 |
1 |
| false |
622 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T3 |
1 |
| true |
429 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T22 |
1 |
| others[1] |
1188 |
1 |
|
T1 |
2 |
|
T2 |
21 |
|
T16 |
1 |
| others[2] |
1173 |
1 |
|
T1 |
3 |
|
T2 |
26 |
|
T3 |
1 |
| others[3] |
2144 |
1 |
|
T1 |
3 |
|
T2 |
30 |
|
T6 |
1 |
| false |
665 |
1 |
|
T1 |
2 |
|
T2 |
10 |
|
T94 |
7 |
| true |
422 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T2 |
4 |
|
T373 |
1 |
|
T390 |
1 |
| others[1] |
98 |
1 |
|
T2 |
2 |
|
T37 |
1 |
|
T38 |
1 |
| others[2] |
111 |
1 |
|
T2 |
4 |
|
T96 |
1 |
|
T370 |
1 |
| others[3] |
176 |
1 |
|
T2 |
4 |
|
T57 |
1 |
|
T96 |
1 |
| false |
57 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T368 |
1 |
| true |
6296 |
1 |
|
T1 |
13 |
|
T2 |
86 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T2 |
10 |
|
T204 |
1 |
|
T35 |
1 |
| others[1] |
221 |
1 |
|
T2 |
9 |
|
T57 |
1 |
|
T177 |
1 |
| others[2] |
208 |
1 |
|
T2 |
7 |
|
T59 |
1 |
|
T27 |
1 |
| others[3] |
370 |
1 |
|
T2 |
21 |
|
T96 |
1 |
|
T25 |
1 |
| false |
109 |
1 |
|
T2 |
5 |
|
T303 |
1 |
|
T28 |
1 |
| true |
5691 |
1 |
|
T1 |
13 |
|
T2 |
49 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1030 |
1 |
|
T1 |
3 |
|
T2 |
17 |
|
T3 |
1 |
| others[1] |
1080 |
1 |
|
T1 |
1 |
|
T2 |
21 |
|
T94 |
17 |
| others[2] |
1035 |
1 |
|
T2 |
23 |
|
T17 |
1 |
|
T121 |
1 |
| others[3] |
1695 |
1 |
|
T1 |
6 |
|
T2 |
26 |
|
T16 |
1 |
| false |
570 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T94 |
7 |
| true |
1415 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T2 |
12 |
|
T20 |
1 |
|
T177 |
1 |
| others[1] |
213 |
1 |
|
T2 |
11 |
|
T32 |
1 |
|
T38 |
1 |
| others[2] |
202 |
1 |
|
T2 |
6 |
|
T379 |
1 |
|
T369 |
1 |
| others[3] |
387 |
1 |
|
T2 |
21 |
|
T17 |
1 |
|
T59 |
1 |
| false |
126 |
1 |
|
T2 |
7 |
|
T25 |
1 |
|
T67 |
1 |
| true |
5687 |
1 |
|
T1 |
13 |
|
T2 |
44 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T2 |
13 |
|
T57 |
1 |
|
T96 |
1 |
| others[1] |
224 |
1 |
|
T2 |
13 |
|
T17 |
1 |
|
T382 |
1 |
| others[2] |
216 |
1 |
|
T2 |
5 |
|
T38 |
1 |
|
T33 |
1 |
| others[3] |
340 |
1 |
|
T2 |
15 |
|
T96 |
1 |
|
T32 |
1 |
| false |
110 |
1 |
|
T2 |
8 |
|
T372 |
1 |
|
T82 |
7 |
| true |
5714 |
1 |
|
T1 |
13 |
|
T2 |
47 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |