Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T1 |
4 |
|
T2 |
13 |
|
T16 |
1 |
| others[1] |
1283 |
1 |
|
T1 |
2 |
|
T2 |
21 |
|
T19 |
1 |
| others[2] |
1191 |
1 |
|
T1 |
2 |
|
T2 |
15 |
|
T3 |
1 |
| others[3] |
2076 |
1 |
|
T1 |
4 |
|
T2 |
37 |
|
T4 |
1 |
| false |
599 |
1 |
|
T1 |
1 |
|
T2 |
15 |
|
T22 |
1 |
| true |
438 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T1 |
3 |
|
T2 |
12 |
|
T94 |
24 |
| others[1] |
1227 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
1 |
| others[2] |
1183 |
1 |
|
T1 |
4 |
|
T2 |
19 |
|
T16 |
1 |
| others[3] |
2117 |
1 |
|
T1 |
2 |
|
T2 |
42 |
|
T19 |
1 |
| false |
619 |
1 |
|
T1 |
2 |
|
T2 |
10 |
|
T57 |
1 |
| true |
421 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
83 |
1 |
|
T2 |
9 |
|
T57 |
1 |
|
T96 |
2 |
| others[1] |
99 |
1 |
|
T2 |
5 |
|
T367 |
1 |
|
T373 |
1 |
| others[2] |
94 |
1 |
|
T2 |
2 |
|
T366 |
1 |
|
T367 |
1 |
| others[3] |
173 |
1 |
|
T2 |
4 |
|
T33 |
1 |
|
T368 |
1 |
| false |
47 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T177 |
1 |
| true |
6329 |
1 |
|
T1 |
13 |
|
T2 |
80 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T2 |
8 |
|
T17 |
1 |
|
T26 |
1 |
| others[1] |
209 |
1 |
|
T2 |
6 |
|
T38 |
1 |
|
T27 |
1 |
| others[2] |
202 |
1 |
|
T2 |
11 |
|
T21 |
1 |
|
T204 |
1 |
| others[3] |
388 |
1 |
|
T2 |
14 |
|
T96 |
1 |
|
T67 |
1 |
| false |
123 |
1 |
|
T2 |
6 |
|
T113 |
1 |
|
T35 |
1 |
| true |
5660 |
1 |
|
T1 |
13 |
|
T2 |
56 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1015 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T3 |
1 |
| others[1] |
1075 |
1 |
|
T1 |
4 |
|
T2 |
25 |
|
T94 |
8 |
| others[2] |
1047 |
1 |
|
T1 |
1 |
|
T2 |
15 |
|
T4 |
1 |
| others[3] |
1767 |
1 |
|
T1 |
4 |
|
T2 |
28 |
|
T10 |
1 |
| false |
546 |
1 |
|
T1 |
1 |
|
T2 |
12 |
|
T16 |
1 |
| true |
1375 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T2 |
6 |
|
T177 |
1 |
|
T113 |
1 |
| others[1] |
230 |
1 |
|
T2 |
12 |
|
T32 |
1 |
|
T368 |
1 |
| others[2] |
208 |
1 |
|
T2 |
9 |
|
T20 |
1 |
|
T204 |
1 |
| others[3] |
370 |
1 |
|
T2 |
16 |
|
T6 |
1 |
|
T96 |
1 |
| false |
107 |
1 |
|
T2 |
3 |
|
T192 |
1 |
|
T378 |
1 |
| true |
5704 |
1 |
|
T1 |
13 |
|
T2 |
55 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T2 |
13 |
|
T96 |
1 |
|
T192 |
1 |
| others[1] |
193 |
1 |
|
T2 |
12 |
|
T26 |
1 |
|
T27 |
1 |
| others[2] |
197 |
1 |
|
T2 |
10 |
|
T32 |
1 |
|
T82 |
11 |
| others[3] |
345 |
1 |
|
T2 |
8 |
|
T57 |
1 |
|
T37 |
1 |
| false |
123 |
1 |
|
T2 |
6 |
|
T17 |
1 |
|
T96 |
1 |
| true |
5757 |
1 |
|
T1 |
13 |
|
T2 |
52 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T1 |
3 |
|
T2 |
28 |
|
T36 |
1 |
| others[1] |
1207 |
1 |
|
T1 |
1 |
|
T2 |
20 |
|
T16 |
1 |
| others[2] |
1193 |
1 |
|
T1 |
2 |
|
T2 |
19 |
|
T23 |
1 |
| others[3] |
2100 |
1 |
|
T1 |
5 |
|
T2 |
27 |
|
T3 |
1 |
| false |
645 |
1 |
|
T1 |
2 |
|
T2 |
7 |
|
T19 |
1 |
| true |
447 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T1 |
4 |
|
T2 |
24 |
|
T94 |
21 |
| others[1] |
1234 |
1 |
|
T1 |
3 |
|
T2 |
16 |
|
T4 |
1 |
| others[2] |
1233 |
1 |
|
T1 |
3 |
|
T2 |
18 |
|
T22 |
1 |
| others[3] |
2106 |
1 |
|
T1 |
3 |
|
T2 |
30 |
|
T3 |
1 |
| false |
600 |
1 |
|
T2 |
13 |
|
T16 |
1 |
|
T94 |
13 |
| true |
425 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T2 |
2 |
|
T57 |
1 |
|
T37 |
1 |
| others[1] |
110 |
1 |
|
T2 |
5 |
|
T96 |
1 |
|
T38 |
1 |
| others[2] |
80 |
1 |
|
T2 |
5 |
|
T368 |
1 |
|
T81 |
1 |
| others[3] |
167 |
1 |
|
T2 |
4 |
|
T370 |
1 |
|
T367 |
1 |
| false |
42 |
1 |
|
T96 |
1 |
|
T177 |
1 |
|
T368 |
1 |
| true |
6334 |
1 |
|
T1 |
13 |
|
T2 |
85 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T2 |
7 |
|
T57 |
1 |
|
T177 |
1 |
| others[1] |
250 |
1 |
|
T2 |
11 |
|
T28 |
1 |
|
T81 |
1 |
| others[2] |
210 |
1 |
|
T2 |
9 |
|
T192 |
1 |
|
T33 |
1 |
| others[3] |
371 |
1 |
|
T2 |
18 |
|
T17 |
1 |
|
T21 |
1 |
| false |
124 |
1 |
|
T2 |
6 |
|
T20 |
1 |
|
T96 |
1 |
| true |
5674 |
1 |
|
T1 |
13 |
|
T2 |
50 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1003 |
1 |
|
T1 |
2 |
|
T2 |
27 |
|
T3 |
1 |
| others[1] |
1028 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T23 |
1 |
| others[2] |
1025 |
1 |
|
T1 |
1 |
|
T2 |
24 |
|
T17 |
1 |
| others[3] |
1800 |
1 |
|
T1 |
6 |
|
T2 |
34 |
|
T16 |
1 |
| false |
558 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T4 |
1 |
| true |
1411 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T2 |
11 |
|
T37 |
1 |
|
T59 |
1 |
| others[1] |
202 |
1 |
|
T2 |
7 |
|
T31 |
1 |
|
T366 |
1 |
| others[2] |
206 |
1 |
|
T2 |
11 |
|
T26 |
1 |
|
T113 |
1 |
| others[3] |
377 |
1 |
|
T2 |
20 |
|
T6 |
1 |
|
T57 |
1 |
| false |
122 |
1 |
|
T2 |
6 |
|
T32 |
1 |
|
T114 |
1 |
| true |
5685 |
1 |
|
T1 |
13 |
|
T2 |
46 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
188 |
1 |
|
T2 |
4 |
|
T26 |
1 |
|
T371 |
1 |
| others[1] |
207 |
1 |
|
T2 |
12 |
|
T17 |
1 |
|
T96 |
1 |
| others[2] |
224 |
1 |
|
T2 |
9 |
|
T38 |
1 |
|
T177 |
1 |
| others[3] |
351 |
1 |
|
T2 |
15 |
|
T32 |
1 |
|
T378 |
1 |
| false |
107 |
1 |
|
T2 |
4 |
|
T369 |
1 |
|
T374 |
1 |
| true |
5748 |
1 |
|
T1 |
13 |
|
T2 |
57 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1205 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T36 |
1 |
| others[1] |
1222 |
1 |
|
T1 |
4 |
|
T2 |
16 |
|
T17 |
1 |
| others[2] |
1247 |
1 |
|
T1 |
1 |
|
T2 |
15 |
|
T16 |
1 |
| others[3] |
2090 |
1 |
|
T1 |
5 |
|
T2 |
44 |
|
T6 |
1 |
| false |
634 |
1 |
|
T1 |
2 |
|
T2 |
9 |
|
T3 |
1 |
| true |
427 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T1 |
2 |
|
T2 |
16 |
|
T94 |
19 |
| others[1] |
1209 |
1 |
|
T1 |
1 |
|
T2 |
23 |
|
T3 |
1 |
| others[2] |
1224 |
1 |
|
T1 |
4 |
|
T2 |
18 |
|
T16 |
1 |
| others[3] |
2105 |
1 |
|
T1 |
5 |
|
T2 |
34 |
|
T4 |
1 |
| false |
644 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T94 |
9 |
| true |
419 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T2 |
2 |
|
T96 |
1 |
|
T28 |
1 |
| others[1] |
91 |
1 |
|
T2 |
3 |
|
T37 |
1 |
|
T368 |
1 |
| others[2] |
87 |
1 |
|
T2 |
4 |
|
T38 |
1 |
|
T177 |
1 |
| others[3] |
165 |
1 |
|
T2 |
9 |
|
T57 |
1 |
|
T96 |
1 |
| false |
46 |
1 |
|
T2 |
1 |
|
T82 |
1 |
|
T384 |
1 |
| true |
6348 |
1 |
|
T1 |
13 |
|
T2 |
82 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T2 |
12 |
|
T20 |
1 |
|
T192 |
1 |
| others[1] |
242 |
1 |
|
T2 |
15 |
|
T6 |
1 |
|
T37 |
1 |
| others[2] |
221 |
1 |
|
T2 |
10 |
|
T96 |
1 |
|
T38 |
1 |
| others[3] |
369 |
1 |
|
T2 |
18 |
|
T177 |
1 |
|
T24 |
1 |
| false |
104 |
1 |
|
T2 |
3 |
|
T17 |
1 |
|
T96 |
1 |
| true |
5673 |
1 |
|
T1 |
13 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T1 |
3 |
|
T2 |
19 |
|
T3 |
1 |
| others[1] |
1008 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T16 |
1 |
| others[2] |
1129 |
1 |
|
T2 |
16 |
|
T22 |
1 |
|
T121 |
1 |
| others[3] |
1720 |
1 |
|
T1 |
7 |
|
T2 |
38 |
|
T6 |
1 |
| false |
554 |
1 |
|
T1 |
2 |
|
T2 |
15 |
|
T94 |
5 |
| true |
1356 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T2 |
11 |
|
T34 |
1 |
|
T93 |
1 |
| others[1] |
218 |
1 |
|
T2 |
11 |
|
T6 |
1 |
|
T25 |
1 |
| others[2] |
238 |
1 |
|
T2 |
14 |
|
T96 |
1 |
|
T89 |
1 |
| others[3] |
339 |
1 |
|
T2 |
10 |
|
T20 |
1 |
|
T192 |
1 |
| false |
111 |
1 |
|
T2 |
8 |
|
T378 |
1 |
|
T210 |
1 |
| true |
5693 |
1 |
|
T1 |
13 |
|
T2 |
47 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
8 |
|
T27 |
1 |
|
T33 |
1 |
| others[1] |
218 |
1 |
|
T2 |
9 |
|
T37 |
1 |
|
T28 |
1 |
| others[2] |
204 |
1 |
|
T2 |
13 |
|
T32 |
1 |
|
T49 |
1 |
| others[3] |
366 |
1 |
|
T2 |
10 |
|
T96 |
2 |
|
T192 |
1 |
| false |
113 |
1 |
|
T2 |
3 |
|
T81 |
1 |
|
T134 |
1 |
| true |
5706 |
1 |
|
T1 |
13 |
|
T2 |
58 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1158 |
1 |
|
T2 |
14 |
|
T53 |
1 |
|
T57 |
1 |
| others[1] |
1257 |
1 |
|
T1 |
7 |
|
T2 |
21 |
|
T3 |
1 |
| others[2] |
1235 |
1 |
|
T1 |
2 |
|
T2 |
19 |
|
T23 |
1 |
| others[3] |
2075 |
1 |
|
T1 |
4 |
|
T2 |
36 |
|
T16 |
1 |
| false |
665 |
1 |
|
T2 |
11 |
|
T22 |
1 |
|
T94 |
7 |
| true |
435 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1190 |
1 |
|
T1 |
1 |
|
T2 |
28 |
|
T36 |
1 |
| others[1] |
1221 |
1 |
|
T1 |
7 |
|
T2 |
17 |
|
T94 |
16 |
| others[2] |
1212 |
1 |
|
T1 |
2 |
|
T2 |
17 |
|
T19 |
1 |
| others[3] |
2119 |
1 |
|
T1 |
3 |
|
T2 |
34 |
|
T3 |
1 |
| false |
656 |
1 |
|
T2 |
5 |
|
T4 |
1 |
|
T23 |
1 |
| true |
427 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T2 |
6 |
|
T57 |
1 |
|
T96 |
1 |
| others[1] |
98 |
1 |
|
T2 |
5 |
|
T96 |
1 |
|
T37 |
1 |
| others[2] |
105 |
1 |
|
T2 |
6 |
|
T366 |
1 |
|
T367 |
1 |
| others[3] |
173 |
1 |
|
T2 |
6 |
|
T89 |
1 |
|
T368 |
1 |
| false |
44 |
1 |
|
T2 |
2 |
|
T177 |
1 |
|
T376 |
1 |
| true |
6307 |
1 |
|
T1 |
13 |
|
T2 |
76 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T2 |
11 |
|
T57 |
1 |
|
T59 |
1 |
| others[1] |
225 |
1 |
|
T2 |
9 |
|
T113 |
1 |
|
T33 |
1 |
| others[2] |
206 |
1 |
|
T2 |
15 |
|
T96 |
1 |
|
T177 |
1 |
| others[3] |
362 |
1 |
|
T2 |
25 |
|
T32 |
1 |
|
T38 |
1 |
| false |
119 |
1 |
|
T2 |
2 |
|
T49 |
1 |
|
T369 |
1 |
| true |
5687 |
1 |
|
T1 |
13 |
|
T2 |
39 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T5 |
1 |
| others[1] |
1016 |
1 |
|
T1 |
4 |
|
T2 |
26 |
|
T4 |
1 |
| others[2] |
1055 |
1 |
|
T1 |
4 |
|
T2 |
25 |
|
T3 |
1 |
| others[3] |
1757 |
1 |
|
T1 |
1 |
|
T2 |
29 |
|
T16 |
1 |
| false |
527 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T19 |
1 |
| true |
1424 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T2 |
15 |
|
T96 |
1 |
|
T89 |
1 |
| others[1] |
228 |
1 |
|
T2 |
7 |
|
T37 |
1 |
|
T133 |
1 |
| others[2] |
221 |
1 |
|
T2 |
18 |
|
T32 |
1 |
|
T38 |
1 |
| others[3] |
346 |
1 |
|
T2 |
14 |
|
T59 |
1 |
|
T26 |
1 |
| false |
112 |
1 |
|
T2 |
2 |
|
T60 |
1 |
|
T391 |
1 |
| true |
5687 |
1 |
|
T1 |
13 |
|
T2 |
45 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T2 |
10 |
|
T366 |
1 |
|
T391 |
1 |
| others[1] |
212 |
1 |
|
T2 |
6 |
|
T17 |
1 |
|
T27 |
1 |
| others[2] |
202 |
1 |
|
T2 |
12 |
|
T37 |
1 |
|
T26 |
1 |
| others[3] |
339 |
1 |
|
T2 |
15 |
|
T57 |
1 |
|
T96 |
1 |
| false |
95 |
1 |
|
T2 |
5 |
|
T369 |
1 |
|
T386 |
1 |
| true |
5778 |
1 |
|
T1 |
13 |
|
T2 |
53 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T1 |
2 |
|
T2 |
16 |
|
T23 |
1 |
| others[1] |
1255 |
1 |
|
T1 |
2 |
|
T2 |
20 |
|
T16 |
1 |
| others[2] |
1205 |
1 |
|
T1 |
1 |
|
T2 |
25 |
|
T36 |
1 |
| others[3] |
2057 |
1 |
|
T1 |
5 |
|
T2 |
25 |
|
T3 |
1 |
| false |
653 |
1 |
|
T1 |
3 |
|
T2 |
15 |
|
T94 |
9 |
| true |
432 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T1 |
3 |
|
T2 |
24 |
|
T4 |
1 |
| others[1] |
1200 |
1 |
|
T1 |
2 |
|
T2 |
17 |
|
T121 |
1 |
| others[2] |
1262 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T94 |
22 |
| others[3] |
2042 |
1 |
|
T1 |
5 |
|
T2 |
34 |
|
T3 |
1 |
| false |
638 |
1 |
|
T1 |
2 |
|
T2 |
9 |
|
T36 |
1 |
| true |
410 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T2 |
2 |
|
T96 |
1 |
|
T37 |
1 |
| others[1] |
99 |
1 |
|
T2 |
4 |
|
T367 |
1 |
|
T373 |
1 |
| others[2] |
90 |
1 |
|
T2 |
2 |
|
T96 |
1 |
|
T368 |
2 |
| others[3] |
135 |
1 |
|
T2 |
6 |
|
T38 |
1 |
|
T26 |
1 |
| false |
62 |
1 |
|
T2 |
2 |
|
T81 |
1 |
|
T370 |
1 |
| true |
6338 |
1 |
|
T1 |
13 |
|
T2 |
85 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |