Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T2 |
6 |
|
T37 |
1 |
|
T113 |
1 |
| others[1] |
207 |
1 |
|
T2 |
9 |
|
T57 |
1 |
|
T27 |
1 |
| others[2] |
243 |
1 |
|
T2 |
11 |
|
T6 |
1 |
|
T17 |
1 |
| others[3] |
386 |
1 |
|
T2 |
22 |
|
T96 |
1 |
|
T26 |
1 |
| false |
126 |
1 |
|
T2 |
9 |
|
T388 |
1 |
|
T100 |
1 |
| true |
5637 |
1 |
|
T1 |
13 |
|
T2 |
44 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1021 |
1 |
|
T1 |
2 |
|
T2 |
23 |
|
T121 |
1 |
| others[1] |
1046 |
1 |
|
T1 |
5 |
|
T2 |
22 |
|
T6 |
1 |
| others[2] |
1041 |
1 |
|
T1 |
1 |
|
T2 |
19 |
|
T3 |
1 |
| others[3] |
1762 |
1 |
|
T1 |
4 |
|
T2 |
29 |
|
T10 |
1 |
| false |
589 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T23 |
1 |
| true |
1366 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T94 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
192 |
1 |
|
T2 |
11 |
|
T33 |
1 |
|
T378 |
1 |
| others[1] |
228 |
1 |
|
T2 |
13 |
|
T6 |
1 |
|
T38 |
1 |
| others[2] |
221 |
1 |
|
T2 |
9 |
|
T17 |
1 |
|
T25 |
1 |
| others[3] |
362 |
1 |
|
T2 |
15 |
|
T59 |
1 |
|
T114 |
1 |
| false |
124 |
1 |
|
T2 |
7 |
|
T20 |
1 |
|
T366 |
1 |
| true |
5698 |
1 |
|
T1 |
13 |
|
T2 |
46 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
7 |
|
T17 |
1 |
|
T33 |
1 |
| others[1] |
215 |
1 |
|
T2 |
13 |
|
T96 |
1 |
|
T382 |
1 |
| others[2] |
227 |
1 |
|
T2 |
14 |
|
T32 |
1 |
|
T177 |
1 |
| others[3] |
332 |
1 |
|
T2 |
19 |
|
T96 |
1 |
|
T368 |
1 |
| false |
100 |
1 |
|
T2 |
7 |
|
T28 |
1 |
|
T383 |
1 |
| true |
5733 |
1 |
|
T1 |
13 |
|
T2 |
41 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T1 |
2 |
|
T2 |
24 |
|
T22 |
1 |
| others[1] |
1207 |
1 |
|
T2 |
16 |
|
T36 |
1 |
|
T94 |
22 |
| others[2] |
1241 |
1 |
|
T1 |
3 |
|
T2 |
19 |
|
T4 |
1 |
| others[3] |
2055 |
1 |
|
T1 |
7 |
|
T2 |
28 |
|
T3 |
1 |
| false |
643 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T94 |
7 |
| true |
443 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1175 |
1 |
|
T1 |
3 |
|
T2 |
15 |
|
T36 |
1 |
| others[1] |
1235 |
1 |
|
T1 |
3 |
|
T2 |
25 |
|
T3 |
1 |
| others[2] |
1239 |
1 |
|
T1 |
5 |
|
T2 |
17 |
|
T53 |
1 |
| others[3] |
2074 |
1 |
|
T1 |
2 |
|
T2 |
29 |
|
T10 |
1 |
| false |
684 |
1 |
|
T2 |
15 |
|
T22 |
1 |
|
T94 |
11 |
| true |
418 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
84 |
1 |
|
T2 |
2 |
|
T383 |
1 |
|
T372 |
1 |
| others[1] |
82 |
1 |
|
T2 |
2 |
|
T38 |
1 |
|
T366 |
1 |
| others[2] |
95 |
1 |
|
T2 |
2 |
|
T96 |
1 |
|
T177 |
1 |
| others[3] |
146 |
1 |
|
T2 |
5 |
|
T57 |
1 |
|
T37 |
1 |
| false |
51 |
1 |
|
T96 |
1 |
|
T376 |
1 |
|
T82 |
2 |
| true |
6367 |
1 |
|
T1 |
13 |
|
T2 |
90 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T2 |
7 |
|
T20 |
1 |
|
T192 |
1 |
| others[1] |
233 |
1 |
|
T2 |
11 |
|
T32 |
1 |
|
T113 |
1 |
| others[2] |
213 |
1 |
|
T2 |
7 |
|
T25 |
1 |
|
T38 |
1 |
| others[3] |
366 |
1 |
|
T2 |
17 |
|
T272 |
1 |
|
T268 |
1 |
| false |
111 |
1 |
|
T2 |
3 |
|
T57 |
1 |
|
T21 |
1 |
| true |
5674 |
1 |
|
T1 |
13 |
|
T2 |
56 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T19 |
1 |
| others[1] |
1074 |
1 |
|
T1 |
2 |
|
T2 |
22 |
|
T23 |
1 |
| others[2] |
1038 |
1 |
|
T1 |
4 |
|
T2 |
21 |
|
T4 |
1 |
| others[3] |
1771 |
1 |
|
T1 |
3 |
|
T2 |
28 |
|
T3 |
1 |
| false |
540 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T16 |
1 |
| true |
1361 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T2 |
8 |
|
T6 |
1 |
|
T93 |
1 |
| others[1] |
255 |
1 |
|
T2 |
14 |
|
T57 |
1 |
|
T81 |
1 |
| others[2] |
220 |
1 |
|
T2 |
10 |
|
T17 |
1 |
|
T37 |
1 |
| others[3] |
334 |
1 |
|
T2 |
14 |
|
T20 |
1 |
|
T96 |
1 |
| false |
126 |
1 |
|
T2 |
7 |
|
T376 |
1 |
|
T82 |
5 |
| true |
5650 |
1 |
|
T1 |
13 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
6 |
|
T96 |
1 |
|
T368 |
1 |
| others[1] |
201 |
1 |
|
T2 |
8 |
|
T89 |
1 |
|
T373 |
1 |
| others[2] |
189 |
1 |
|
T2 |
11 |
|
T17 |
1 |
|
T38 |
1 |
| others[3] |
348 |
1 |
|
T2 |
20 |
|
T27 |
1 |
|
T33 |
1 |
| false |
101 |
1 |
|
T2 |
6 |
|
T28 |
1 |
|
T253 |
1 |
| true |
5768 |
1 |
|
T1 |
13 |
|
T2 |
50 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1306 |
1 |
|
T1 |
5 |
|
T2 |
29 |
|
T17 |
1 |
| others[1] |
1254 |
1 |
|
T1 |
2 |
|
T2 |
20 |
|
T53 |
1 |
| others[2] |
1161 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T16 |
1 |
| others[3] |
2019 |
1 |
|
T1 |
2 |
|
T2 |
29 |
|
T3 |
1 |
| false |
652 |
1 |
|
T1 |
3 |
|
T2 |
9 |
|
T94 |
9 |
| true |
433 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T1 |
1 |
|
T2 |
24 |
|
T4 |
1 |
| others[1] |
1243 |
1 |
|
T1 |
5 |
|
T2 |
13 |
|
T19 |
1 |
| others[2] |
1171 |
1 |
|
T1 |
3 |
|
T2 |
28 |
|
T16 |
1 |
| others[3] |
2110 |
1 |
|
T1 |
4 |
|
T2 |
28 |
|
T3 |
1 |
| false |
648 |
1 |
|
T2 |
8 |
|
T57 |
1 |
|
T94 |
10 |
| true |
427 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T2 |
1 |
|
T96 |
1 |
|
T369 |
1 |
| others[1] |
90 |
1 |
|
T2 |
4 |
|
T38 |
1 |
|
T392 |
1 |
| others[2] |
95 |
1 |
|
T2 |
8 |
|
T37 |
1 |
|
T372 |
1 |
| others[3] |
148 |
1 |
|
T2 |
4 |
|
T96 |
1 |
|
T177 |
1 |
| false |
58 |
1 |
|
T2 |
3 |
|
T57 |
1 |
|
T210 |
1 |
| true |
6334 |
1 |
|
T1 |
13 |
|
T2 |
81 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T2 |
11 |
|
T6 |
1 |
|
T25 |
1 |
| others[1] |
281 |
1 |
|
T2 |
12 |
|
T89 |
1 |
|
T368 |
2 |
| others[2] |
207 |
1 |
|
T2 |
8 |
|
T37 |
1 |
|
T26 |
1 |
| others[3] |
386 |
1 |
|
T2 |
20 |
|
T17 |
1 |
|
T21 |
1 |
| false |
93 |
1 |
|
T2 |
2 |
|
T57 |
1 |
|
T96 |
1 |
| true |
5641 |
1 |
|
T1 |
13 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1060 |
1 |
|
T1 |
4 |
|
T2 |
23 |
|
T16 |
1 |
| others[1] |
990 |
1 |
|
T2 |
14 |
|
T10 |
1 |
|
T94 |
8 |
| others[2] |
1091 |
1 |
|
T1 |
3 |
|
T2 |
15 |
|
T4 |
1 |
| others[3] |
1779 |
1 |
|
T1 |
4 |
|
T2 |
39 |
|
T3 |
1 |
| false |
556 |
1 |
|
T1 |
2 |
|
T2 |
10 |
|
T23 |
1 |
| true |
1349 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T121 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T2 |
13 |
|
T37 |
1 |
|
T113 |
1 |
| others[1] |
218 |
1 |
|
T2 |
6 |
|
T38 |
1 |
|
T93 |
1 |
| others[2] |
216 |
1 |
|
T2 |
11 |
|
T33 |
1 |
|
T114 |
1 |
| others[3] |
324 |
1 |
|
T2 |
22 |
|
T177 |
1 |
|
T34 |
1 |
| false |
123 |
1 |
|
T2 |
6 |
|
T57 |
1 |
|
T96 |
1 |
| true |
5732 |
1 |
|
T1 |
13 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T2 |
4 |
|
T38 |
1 |
|
T177 |
1 |
| others[1] |
190 |
1 |
|
T2 |
8 |
|
T57 |
1 |
|
T366 |
1 |
| others[2] |
192 |
1 |
|
T2 |
13 |
|
T371 |
1 |
|
T7 |
2 |
| others[3] |
357 |
1 |
|
T2 |
13 |
|
T378 |
1 |
|
T392 |
1 |
| false |
114 |
1 |
|
T2 |
7 |
|
T269 |
1 |
|
T393 |
1 |
| true |
5766 |
1 |
|
T1 |
13 |
|
T2 |
56 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T1 |
1 |
|
T2 |
25 |
|
T23 |
1 |
| others[1] |
1189 |
1 |
|
T1 |
1 |
|
T2 |
21 |
|
T94 |
12 |
| others[2] |
1246 |
1 |
|
T1 |
5 |
|
T2 |
17 |
|
T16 |
1 |
| others[3] |
2053 |
1 |
|
T1 |
3 |
|
T2 |
29 |
|
T3 |
1 |
| false |
659 |
1 |
|
T1 |
3 |
|
T2 |
9 |
|
T57 |
1 |
| true |
431 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T1 |
3 |
|
T2 |
18 |
|
T16 |
1 |
| others[1] |
1281 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T10 |
1 |
| others[2] |
1155 |
1 |
|
T1 |
4 |
|
T2 |
18 |
|
T3 |
1 |
| others[3] |
2059 |
1 |
|
T1 |
3 |
|
T2 |
37 |
|
T19 |
1 |
| false |
622 |
1 |
|
T1 |
2 |
|
T2 |
14 |
|
T94 |
7 |
| true |
431 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T2 |
4 |
|
T210 |
1 |
|
T367 |
1 |
| others[1] |
87 |
1 |
|
T2 |
5 |
|
T177 |
1 |
|
T367 |
1 |
| others[2] |
99 |
1 |
|
T2 |
4 |
|
T37 |
1 |
|
T82 |
6 |
| others[3] |
157 |
1 |
|
T2 |
5 |
|
T96 |
2 |
|
T38 |
1 |
| false |
51 |
1 |
|
T2 |
2 |
|
T57 |
1 |
|
T368 |
1 |
| true |
6323 |
1 |
|
T1 |
13 |
|
T2 |
81 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T2 |
6 |
|
T114 |
1 |
|
T378 |
1 |
| others[1] |
244 |
1 |
|
T2 |
9 |
|
T96 |
1 |
|
T303 |
1 |
| others[2] |
206 |
1 |
|
T2 |
7 |
|
T32 |
1 |
|
T26 |
1 |
| others[3] |
314 |
1 |
|
T2 |
8 |
|
T59 |
1 |
|
T34 |
1 |
| false |
114 |
1 |
|
T2 |
8 |
|
T204 |
1 |
|
T368 |
1 |
| true |
5736 |
1 |
|
T1 |
13 |
|
T2 |
63 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1033 |
1 |
|
T1 |
3 |
|
T2 |
24 |
|
T10 |
1 |
| others[1] |
1034 |
1 |
|
T1 |
2 |
|
T2 |
17 |
|
T36 |
1 |
| others[2] |
1036 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T53 |
1 |
| others[3] |
1790 |
1 |
|
T1 |
6 |
|
T2 |
30 |
|
T3 |
1 |
| false |
547 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T4 |
1 |
| true |
1385 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T94 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T2 |
11 |
|
T37 |
1 |
|
T81 |
1 |
| others[1] |
198 |
1 |
|
T2 |
11 |
|
T20 |
1 |
|
T57 |
1 |
| others[2] |
227 |
1 |
|
T2 |
7 |
|
T204 |
1 |
|
T382 |
1 |
| others[3] |
349 |
1 |
|
T2 |
15 |
|
T6 |
1 |
|
T17 |
1 |
| false |
100 |
1 |
|
T2 |
6 |
|
T114 |
1 |
|
T82 |
7 |
| true |
5730 |
1 |
|
T1 |
13 |
|
T2 |
51 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T2 |
14 |
|
T96 |
1 |
|
T368 |
1 |
| others[1] |
201 |
1 |
|
T2 |
12 |
|
T17 |
1 |
|
T57 |
1 |
| others[2] |
232 |
1 |
|
T2 |
9 |
|
T38 |
1 |
|
T368 |
1 |
| others[3] |
339 |
1 |
|
T2 |
16 |
|
T89 |
1 |
|
T27 |
1 |
| false |
98 |
1 |
|
T2 |
7 |
|
T82 |
5 |
|
T394 |
1 |
| true |
5726 |
1 |
|
T1 |
13 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T94 |
22 |
| others[1] |
1274 |
1 |
|
T1 |
4 |
|
T2 |
17 |
|
T4 |
1 |
| others[2] |
1202 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T121 |
1 |
| others[3] |
2058 |
1 |
|
T1 |
6 |
|
T2 |
39 |
|
T3 |
1 |
| false |
620 |
1 |
|
T2 |
10 |
|
T53 |
1 |
|
T94 |
14 |
| true |
430 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1178 |
1 |
|
T1 |
1 |
|
T2 |
21 |
|
T16 |
1 |
| others[1] |
1239 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T6 |
1 |
| others[2] |
1252 |
1 |
|
T1 |
4 |
|
T2 |
20 |
|
T3 |
1 |
| others[3] |
2085 |
1 |
|
T1 |
5 |
|
T2 |
34 |
|
T19 |
1 |
| false |
650 |
1 |
|
T2 |
12 |
|
T4 |
1 |
|
T94 |
8 |
| true |
421 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T2 |
7 |
|
T366 |
1 |
|
T367 |
1 |
| others[1] |
87 |
1 |
|
T2 |
5 |
|
T96 |
1 |
|
T177 |
1 |
| others[2] |
95 |
1 |
|
T2 |
6 |
|
T37 |
1 |
|
T368 |
1 |
| others[3] |
143 |
1 |
|
T2 |
4 |
|
T26 |
1 |
|
T133 |
1 |
| false |
48 |
1 |
|
T2 |
1 |
|
T96 |
1 |
|
T38 |
1 |
| true |
6355 |
1 |
|
T1 |
13 |
|
T2 |
78 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T2 |
14 |
|
T96 |
1 |
|
T34 |
1 |
| others[1] |
224 |
1 |
|
T2 |
14 |
|
T368 |
1 |
|
T81 |
1 |
| others[2] |
216 |
1 |
|
T2 |
9 |
|
T17 |
1 |
|
T21 |
1 |
| others[3] |
375 |
1 |
|
T2 |
14 |
|
T96 |
1 |
|
T32 |
1 |
| false |
118 |
1 |
|
T2 |
2 |
|
T114 |
1 |
|
T386 |
1 |
| true |
5646 |
1 |
|
T1 |
13 |
|
T2 |
48 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T1 |
3 |
|
T2 |
17 |
|
T3 |
1 |
| others[1] |
1018 |
1 |
|
T1 |
3 |
|
T2 |
15 |
|
T17 |
1 |
| others[2] |
1030 |
1 |
|
T1 |
4 |
|
T2 |
26 |
|
T4 |
1 |
| others[3] |
1712 |
1 |
|
T1 |
1 |
|
T2 |
35 |
|
T16 |
1 |
| false |
553 |
1 |
|
T1 |
2 |
|
T2 |
8 |
|
T53 |
1 |
| true |
1460 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T2 |
13 |
|
T113 |
1 |
|
T89 |
1 |
| others[1] |
213 |
1 |
|
T2 |
7 |
|
T49 |
1 |
|
T268 |
1 |
| others[2] |
207 |
1 |
|
T2 |
13 |
|
T31 |
1 |
|
T269 |
1 |
| others[3] |
371 |
1 |
|
T2 |
12 |
|
T17 |
1 |
|
T37 |
1 |
| false |
121 |
1 |
|
T2 |
6 |
|
T6 |
1 |
|
T96 |
1 |
| true |
5710 |
1 |
|
T1 |
13 |
|
T2 |
50 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |