Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
190 |
1 |
|
T2 |
5 |
|
T192 |
1 |
|
T372 |
1 |
| others[1] |
202 |
1 |
|
T2 |
8 |
|
T37 |
1 |
|
T26 |
1 |
| others[2] |
231 |
1 |
|
T2 |
12 |
|
T33 |
1 |
|
T382 |
1 |
| others[3] |
341 |
1 |
|
T2 |
16 |
|
T177 |
1 |
|
T28 |
1 |
| false |
115 |
1 |
|
T2 |
9 |
|
T27 |
1 |
|
T378 |
1 |
| true |
5746 |
1 |
|
T1 |
13 |
|
T2 |
51 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T1 |
3 |
|
T2 |
18 |
|
T4 |
1 |
| others[1] |
1188 |
1 |
|
T1 |
1 |
|
T2 |
23 |
|
T22 |
1 |
| others[2] |
1212 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T3 |
1 |
| others[3] |
2045 |
1 |
|
T1 |
6 |
|
T2 |
37 |
|
T17 |
1 |
| false |
679 |
1 |
|
T2 |
9 |
|
T53 |
1 |
|
T57 |
1 |
| true |
442 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1193 |
1 |
|
T1 |
3 |
|
T2 |
18 |
|
T3 |
1 |
| others[1] |
1209 |
1 |
|
T1 |
2 |
|
T2 |
22 |
|
T4 |
1 |
| others[2] |
1249 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T22 |
1 |
| others[3] |
2125 |
1 |
|
T1 |
6 |
|
T2 |
35 |
|
T16 |
1 |
| false |
627 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T57 |
1 |
| true |
422 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T2 |
6 |
|
T96 |
1 |
|
T38 |
1 |
| others[1] |
95 |
1 |
|
T2 |
1 |
|
T96 |
1 |
|
T177 |
1 |
| others[2] |
87 |
1 |
|
T2 |
1 |
|
T368 |
1 |
|
T366 |
1 |
| others[3] |
149 |
1 |
|
T2 |
8 |
|
T37 |
1 |
|
T366 |
1 |
| false |
44 |
1 |
|
T382 |
1 |
|
T370 |
1 |
|
T372 |
1 |
| true |
6353 |
1 |
|
T1 |
13 |
|
T2 |
85 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T2 |
15 |
|
T6 |
1 |
|
T96 |
1 |
| others[1] |
229 |
1 |
|
T2 |
10 |
|
T57 |
1 |
|
T59 |
1 |
| others[2] |
211 |
1 |
|
T2 |
5 |
|
T37 |
1 |
|
T89 |
1 |
| others[3] |
380 |
1 |
|
T2 |
22 |
|
T20 |
1 |
|
T192 |
1 |
| false |
122 |
1 |
|
T2 |
4 |
|
T96 |
1 |
|
T27 |
1 |
| true |
5664 |
1 |
|
T1 |
13 |
|
T2 |
45 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T121 |
1 |
| others[1] |
1105 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T16 |
1 |
| others[2] |
1033 |
1 |
|
T1 |
3 |
|
T2 |
22 |
|
T10 |
1 |
| others[3] |
1692 |
1 |
|
T1 |
3 |
|
T2 |
37 |
|
T3 |
1 |
| false |
521 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T4 |
1 |
| true |
1439 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T2 |
12 |
|
T57 |
1 |
|
T38 |
1 |
| others[1] |
218 |
1 |
|
T2 |
15 |
|
T6 |
1 |
|
T37 |
1 |
| others[2] |
204 |
1 |
|
T2 |
9 |
|
T33 |
1 |
|
T114 |
1 |
| others[3] |
388 |
1 |
|
T2 |
16 |
|
T96 |
1 |
|
T25 |
1 |
| false |
99 |
1 |
|
T2 |
5 |
|
T34 |
1 |
|
T367 |
1 |
| true |
5671 |
1 |
|
T1 |
13 |
|
T2 |
44 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T2 |
6 |
|
T96 |
1 |
|
T33 |
1 |
| others[1] |
221 |
1 |
|
T2 |
11 |
|
T81 |
1 |
|
T269 |
1 |
| others[2] |
223 |
1 |
|
T2 |
5 |
|
T28 |
1 |
|
T386 |
1 |
| others[3] |
344 |
1 |
|
T2 |
20 |
|
T96 |
1 |
|
T38 |
1 |
| false |
115 |
1 |
|
T2 |
4 |
|
T177 |
1 |
|
T192 |
1 |
| true |
5705 |
1 |
|
T1 |
13 |
|
T2 |
55 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T1 |
3 |
|
T2 |
24 |
|
T23 |
1 |
| others[1] |
1261 |
1 |
|
T1 |
3 |
|
T2 |
19 |
|
T3 |
1 |
| others[2] |
1253 |
1 |
|
T1 |
2 |
|
T2 |
24 |
|
T22 |
1 |
| others[3] |
2028 |
1 |
|
T1 |
4 |
|
T2 |
24 |
|
T16 |
1 |
| false |
596 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T19 |
1 |
| true |
442 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T1 |
3 |
|
T2 |
23 |
|
T4 |
1 |
| others[1] |
1185 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T121 |
1 |
| others[2] |
1244 |
1 |
|
T1 |
2 |
|
T2 |
23 |
|
T19 |
1 |
| others[3] |
2086 |
1 |
|
T1 |
6 |
|
T2 |
24 |
|
T3 |
1 |
| false |
630 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T10 |
1 |
| true |
417 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T2 |
5 |
|
T96 |
1 |
|
T368 |
1 |
| others[1] |
120 |
1 |
|
T2 |
4 |
|
T38 |
1 |
|
T177 |
1 |
| others[2] |
101 |
1 |
|
T2 |
4 |
|
T57 |
1 |
|
T37 |
1 |
| others[3] |
166 |
1 |
|
T2 |
7 |
|
T96 |
1 |
|
T368 |
1 |
| false |
45 |
1 |
|
T2 |
1 |
|
T366 |
1 |
|
T369 |
1 |
| true |
6285 |
1 |
|
T1 |
13 |
|
T2 |
80 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T2 |
3 |
|
T20 |
1 |
|
T67 |
1 |
| others[1] |
212 |
1 |
|
T2 |
15 |
|
T6 |
1 |
|
T21 |
1 |
| others[2] |
227 |
1 |
|
T2 |
12 |
|
T17 |
1 |
|
T113 |
1 |
| others[3] |
375 |
1 |
|
T2 |
15 |
|
T57 |
1 |
|
T34 |
1 |
| false |
123 |
1 |
|
T2 |
10 |
|
T37 |
1 |
|
T28 |
1 |
| true |
5690 |
1 |
|
T1 |
13 |
|
T2 |
46 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T1 |
1 |
|
T2 |
24 |
|
T16 |
1 |
| others[1] |
1011 |
1 |
|
T1 |
2 |
|
T2 |
15 |
|
T94 |
11 |
| others[2] |
1031 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T4 |
1 |
| others[3] |
1746 |
1 |
|
T1 |
3 |
|
T2 |
34 |
|
T17 |
1 |
| false |
565 |
1 |
|
T1 |
4 |
|
T2 |
14 |
|
T3 |
1 |
| true |
1404 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T2 |
8 |
|
T59 |
1 |
|
T113 |
1 |
| others[1] |
209 |
1 |
|
T2 |
9 |
|
T114 |
1 |
|
T367 |
1 |
| others[2] |
217 |
1 |
|
T2 |
9 |
|
T17 |
1 |
|
T378 |
1 |
| others[3] |
372 |
1 |
|
T2 |
17 |
|
T96 |
2 |
|
T25 |
1 |
| false |
112 |
1 |
|
T2 |
6 |
|
T6 |
1 |
|
T20 |
1 |
| true |
5706 |
1 |
|
T1 |
13 |
|
T2 |
52 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
11 |
|
T383 |
1 |
|
T380 |
1 |
| others[1] |
198 |
1 |
|
T2 |
8 |
|
T33 |
1 |
|
T49 |
1 |
| others[2] |
245 |
1 |
|
T2 |
15 |
|
T17 |
1 |
|
T27 |
1 |
| others[3] |
327 |
1 |
|
T2 |
19 |
|
T38 |
1 |
|
T366 |
1 |
| false |
122 |
1 |
|
T2 |
5 |
|
T32 |
1 |
|
T26 |
1 |
| true |
5715 |
1 |
|
T1 |
13 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T57 |
1 |
| others[1] |
1217 |
1 |
|
T1 |
1 |
|
T2 |
23 |
|
T53 |
1 |
| others[2] |
1219 |
1 |
|
T1 |
5 |
|
T2 |
16 |
|
T10 |
1 |
| others[3] |
2097 |
1 |
|
T1 |
4 |
|
T2 |
32 |
|
T3 |
1 |
| false |
639 |
1 |
|
T1 |
3 |
|
T2 |
8 |
|
T19 |
1 |
| true |
431 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T1 |
4 |
|
T2 |
24 |
|
T6 |
1 |
| others[1] |
1249 |
1 |
|
T1 |
1 |
|
T2 |
21 |
|
T57 |
1 |
| others[2] |
1162 |
1 |
|
T1 |
4 |
|
T2 |
17 |
|
T10 |
1 |
| others[3] |
2060 |
1 |
|
T1 |
3 |
|
T2 |
29 |
|
T3 |
1 |
| false |
645 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T94 |
11 |
| true |
431 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T2 |
3 |
|
T96 |
1 |
|
T38 |
1 |
| others[1] |
87 |
1 |
|
T2 |
6 |
|
T82 |
4 |
|
T395 |
1 |
| others[2] |
112 |
1 |
|
T2 |
1 |
|
T96 |
1 |
|
T368 |
1 |
| others[3] |
140 |
1 |
|
T2 |
4 |
|
T177 |
1 |
|
T368 |
1 |
| false |
47 |
1 |
|
T2 |
3 |
|
T37 |
1 |
|
T371 |
1 |
| true |
6336 |
1 |
|
T1 |
13 |
|
T2 |
84 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T2 |
13 |
|
T34 |
1 |
|
T114 |
1 |
| others[1] |
255 |
1 |
|
T2 |
7 |
|
T57 |
1 |
|
T25 |
1 |
| others[2] |
231 |
1 |
|
T2 |
13 |
|
T204 |
1 |
|
T303 |
1 |
| others[3] |
332 |
1 |
|
T2 |
20 |
|
T37 |
1 |
|
T59 |
1 |
| false |
101 |
1 |
|
T2 |
3 |
|
T32 |
1 |
|
T33 |
1 |
| true |
5684 |
1 |
|
T1 |
13 |
|
T2 |
45 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1050 |
1 |
|
T1 |
3 |
|
T2 |
13 |
|
T36 |
1 |
| others[1] |
1023 |
1 |
|
T1 |
2 |
|
T2 |
20 |
|
T3 |
1 |
| others[2] |
1088 |
1 |
|
T1 |
1 |
|
T2 |
26 |
|
T10 |
1 |
| others[3] |
1705 |
1 |
|
T1 |
5 |
|
T2 |
36 |
|
T19 |
1 |
| false |
549 |
1 |
|
T1 |
2 |
|
T2 |
6 |
|
T4 |
1 |
| true |
1410 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T121 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T2 |
8 |
|
T20 |
1 |
|
T396 |
1 |
| others[1] |
223 |
1 |
|
T2 |
12 |
|
T96 |
1 |
|
T25 |
1 |
| others[2] |
231 |
1 |
|
T2 |
10 |
|
T272 |
1 |
|
T268 |
1 |
| others[3] |
352 |
1 |
|
T2 |
12 |
|
T6 |
1 |
|
T57 |
1 |
| false |
102 |
1 |
|
T2 |
6 |
|
T177 |
1 |
|
T113 |
1 |
| true |
5704 |
1 |
|
T1 |
13 |
|
T2 |
53 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
180 |
1 |
|
T2 |
7 |
|
T32 |
1 |
|
T60 |
1 |
| others[1] |
216 |
1 |
|
T2 |
8 |
|
T96 |
1 |
|
T368 |
2 |
| others[2] |
202 |
1 |
|
T2 |
8 |
|
T382 |
1 |
|
T366 |
1 |
| others[3] |
325 |
1 |
|
T2 |
16 |
|
T96 |
1 |
|
T38 |
1 |
| false |
78 |
1 |
|
T2 |
1 |
|
T26 |
1 |
|
T82 |
4 |
| true |
5824 |
1 |
|
T1 |
13 |
|
T2 |
61 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T1 |
1 |
|
T2 |
17 |
|
T4 |
1 |
| others[1] |
1254 |
1 |
|
T1 |
1 |
|
T2 |
20 |
|
T16 |
1 |
| others[2] |
1235 |
1 |
|
T1 |
2 |
|
T2 |
13 |
|
T53 |
1 |
| others[3] |
2046 |
1 |
|
T1 |
5 |
|
T2 |
40 |
|
T3 |
1 |
| false |
623 |
1 |
|
T1 |
4 |
|
T2 |
11 |
|
T36 |
1 |
| true |
439 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T1 |
4 |
|
T2 |
21 |
|
T53 |
1 |
| others[1] |
1165 |
1 |
|
T2 |
19 |
|
T19 |
1 |
|
T23 |
1 |
| others[2] |
1243 |
1 |
|
T1 |
4 |
|
T2 |
23 |
|
T22 |
1 |
| others[3] |
2051 |
1 |
|
T1 |
1 |
|
T2 |
29 |
|
T3 |
1 |
| false |
660 |
1 |
|
T1 |
4 |
|
T2 |
9 |
|
T57 |
1 |
| true |
421 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T2 |
4 |
|
T26 |
1 |
|
T368 |
1 |
| others[1] |
102 |
1 |
|
T2 |
5 |
|
T37 |
1 |
|
T33 |
1 |
| others[2] |
85 |
1 |
|
T2 |
2 |
|
T177 |
1 |
|
T368 |
1 |
| others[3] |
161 |
1 |
|
T2 |
4 |
|
T96 |
2 |
|
T38 |
1 |
| false |
43 |
1 |
|
T2 |
1 |
|
T57 |
1 |
|
T369 |
1 |
| true |
6340 |
1 |
|
T1 |
13 |
|
T2 |
85 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T2 |
9 |
|
T303 |
1 |
|
T35 |
1 |
| others[1] |
224 |
1 |
|
T2 |
9 |
|
T38 |
1 |
|
T81 |
1 |
| others[2] |
207 |
1 |
|
T2 |
11 |
|
T6 |
1 |
|
T26 |
1 |
| others[3] |
362 |
1 |
|
T2 |
22 |
|
T20 |
1 |
|
T32 |
1 |
| false |
113 |
1 |
|
T2 |
7 |
|
T96 |
1 |
|
T24 |
1 |
| true |
5686 |
1 |
|
T1 |
13 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T1 |
1 |
|
T2 |
23 |
|
T17 |
1 |
| others[1] |
1013 |
1 |
|
T1 |
2 |
|
T2 |
19 |
|
T16 |
1 |
| others[2] |
1046 |
1 |
|
T1 |
3 |
|
T2 |
26 |
|
T10 |
1 |
| others[3] |
1796 |
1 |
|
T1 |
6 |
|
T2 |
26 |
|
T3 |
1 |
| false |
545 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T94 |
4 |
| true |
1368 |
1 |
|
T5 |
1 |
|
T121 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T2 |
16 |
|
T177 |
1 |
|
T114 |
1 |
| others[1] |
223 |
1 |
|
T2 |
12 |
|
T96 |
1 |
|
T303 |
1 |
| others[2] |
203 |
1 |
|
T2 |
11 |
|
T113 |
1 |
|
T134 |
1 |
| others[3] |
356 |
1 |
|
T2 |
13 |
|
T59 |
1 |
|
T192 |
1 |
| false |
105 |
1 |
|
T2 |
3 |
|
T373 |
1 |
|
T374 |
1 |
| true |
5700 |
1 |
|
T1 |
13 |
|
T2 |
46 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T2 |
11 |
|
T57 |
1 |
|
T382 |
1 |
| others[1] |
225 |
1 |
|
T2 |
9 |
|
T37 |
1 |
|
T177 |
1 |
| others[2] |
229 |
1 |
|
T2 |
6 |
|
T96 |
1 |
|
T368 |
2 |
| others[3] |
374 |
1 |
|
T2 |
15 |
|
T96 |
1 |
|
T32 |
1 |
| false |
109 |
1 |
|
T2 |
5 |
|
T38 |
1 |
|
T82 |
8 |
| true |
5679 |
1 |
|
T1 |
13 |
|
T2 |
55 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T1 |
3 |
|
T2 |
17 |
|
T3 |
1 |
| others[1] |
1251 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T53 |
1 |
| others[2] |
1201 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T22 |
1 |
| others[3] |
2040 |
1 |
|
T1 |
5 |
|
T2 |
32 |
|
T16 |
1 |
| false |
644 |
1 |
|
T2 |
13 |
|
T19 |
1 |
|
T94 |
6 |
| true |
444 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T397 |
1 |
|
T398 |
1 |
|
T399 |
1 |
| others[1] |
5 |
1 |
|
T75 |
1 |
|
T152 |
1 |
|
T400 |
1 |
| others[2] |
11 |
1 |
|
T155 |
1 |
|
T401 |
1 |
|
T402 |
1 |
| others[3] |
17 |
1 |
|
T5 |
1 |
|
T401 |
2 |
|
T403 |
1 |
| false |
4 |
1 |
|
T91 |
1 |
|
T404 |
1 |
|
T405 |
1 |
| true |
44 |
1 |
|
T126 |
1 |
|
T155 |
1 |
|
T125 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |