Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11286 |
1 |
|
T1 |
2 |
|
T2 |
21 |
|
T19 |
1 |
| others[1] |
792 |
1 |
|
T1 |
3 |
|
T2 |
17 |
|
T4 |
1 |
| others[2] |
785 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
1 |
| others[3] |
1327 |
1 |
|
T1 |
6 |
|
T2 |
36 |
|
T15 |
1 |
| false |
383 |
1 |
|
T2 |
9 |
|
T23 |
1 |
|
T180 |
3 |
| true |
499 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2563 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T16 |
1 |
| others[1] |
2605 |
1 |
|
T1 |
6 |
|
T2 |
11 |
|
T19 |
1 |
| others[2] |
2712 |
1 |
|
T2 |
8 |
|
T22 |
1 |
|
T51 |
32 |
| others[3] |
4284 |
1 |
|
T1 |
6 |
|
T2 |
16 |
|
T4 |
1 |
| false |
1365 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T51 |
17 |
| true |
1543 |
1 |
|
T2 |
49 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10731 |
1 |
|
T2 |
9 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
271 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T19 |
1 |
| others[2] |
247 |
1 |
|
T2 |
6 |
|
T20 |
1 |
|
T25 |
1 |
| others[3] |
438 |
1 |
|
T2 |
15 |
|
T207 |
1 |
|
T89 |
1 |
| false |
128 |
1 |
|
T2 |
5 |
|
T53 |
1 |
|
T192 |
1 |
| true |
3257 |
1 |
|
T1 |
13 |
|
T2 |
55 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10935 |
1 |
|
T1 |
2 |
|
T2 |
7 |
|
T16 |
1 |
| others[1] |
430 |
1 |
|
T1 |
4 |
|
T2 |
13 |
|
T19 |
1 |
| others[2] |
450 |
1 |
|
T1 |
2 |
|
T2 |
12 |
|
T10 |
1 |
| others[3] |
792 |
1 |
|
T1 |
1 |
|
T2 |
18 |
|
T6 |
1 |
| false |
245 |
1 |
|
T2 |
4 |
|
T4 |
1 |
|
T79 |
1 |
| true |
2220 |
1 |
|
T1 |
4 |
|
T2 |
47 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10712 |
1 |
|
T2 |
6 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
259 |
1 |
|
T2 |
12 |
|
T6 |
1 |
|
T32 |
1 |
| others[2] |
207 |
1 |
|
T2 |
11 |
|
T16 |
1 |
|
T19 |
1 |
| others[3] |
422 |
1 |
|
T2 |
14 |
|
T22 |
1 |
|
T57 |
1 |
| false |
138 |
1 |
|
T2 |
9 |
|
T3 |
1 |
|
T177 |
1 |
| true |
3334 |
1 |
|
T1 |
13 |
|
T2 |
49 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10738 |
1 |
|
T2 |
9 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
240 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T17 |
1 |
| others[2] |
213 |
1 |
|
T2 |
10 |
|
T36 |
1 |
|
T96 |
1 |
| others[3] |
418 |
1 |
|
T2 |
15 |
|
T23 |
1 |
|
T57 |
1 |
| false |
151 |
1 |
|
T2 |
12 |
|
T4 |
1 |
|
T192 |
1 |
| true |
3312 |
1 |
|
T1 |
13 |
|
T2 |
48 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11274 |
1 |
|
T1 |
3 |
|
T2 |
18 |
|
T3 |
1 |
| others[1] |
717 |
1 |
|
T1 |
5 |
|
T2 |
19 |
|
T15 |
1 |
| others[2] |
803 |
1 |
|
T1 |
1 |
|
T2 |
16 |
|
T4 |
1 |
| others[3] |
1366 |
1 |
|
T1 |
4 |
|
T2 |
36 |
|
T22 |
1 |
| false |
430 |
1 |
|
T2 |
12 |
|
T16 |
1 |
|
T180 |
5 |
| true |
482 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11206 |
1 |
|
T1 |
2 |
|
T2 |
24 |
|
T6 |
1 |
| others[1] |
830 |
1 |
|
T1 |
2 |
|
T2 |
21 |
|
T16 |
1 |
| others[2] |
765 |
1 |
|
T1 |
3 |
|
T2 |
13 |
|
T15 |
1 |
| others[3] |
1309 |
1 |
|
T1 |
5 |
|
T2 |
34 |
|
T3 |
1 |
| false |
444 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T52 |
1 |
| true |
494 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2544 |
1 |
|
T1 |
5 |
|
T2 |
11 |
|
T19 |
1 |
| others[1] |
2632 |
1 |
|
T1 |
2 |
|
T2 |
8 |
|
T51 |
20 |
| others[2] |
2564 |
1 |
|
T2 |
8 |
|
T51 |
29 |
|
T18 |
49 |
| others[3] |
4461 |
1 |
|
T1 |
5 |
|
T2 |
17 |
|
T3 |
1 |
| false |
1332 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T51 |
11 |
| true |
1515 |
1 |
|
T2 |
55 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10735 |
1 |
|
T2 |
8 |
|
T6 |
1 |
|
T51 |
138 |
| others[1] |
236 |
1 |
|
T2 |
6 |
|
T113 |
1 |
|
T303 |
1 |
| others[2] |
255 |
1 |
|
T2 |
12 |
|
T38 |
1 |
|
T67 |
1 |
| others[3] |
435 |
1 |
|
T2 |
16 |
|
T16 |
1 |
|
T22 |
1 |
| false |
144 |
1 |
|
T2 |
1 |
|
T130 |
1 |
|
T406 |
1 |
| true |
3243 |
1 |
|
T1 |
13 |
|
T2 |
58 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10933 |
1 |
|
T1 |
3 |
|
T2 |
8 |
|
T51 |
138 |
| others[1] |
471 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T11 |
1 |
| others[2] |
470 |
1 |
|
T2 |
12 |
|
T15 |
1 |
|
T4 |
1 |
| others[3] |
734 |
1 |
|
T2 |
16 |
|
T3 |
1 |
|
T6 |
1 |
| false |
254 |
1 |
|
T2 |
5 |
|
T188 |
1 |
|
T180 |
1 |
| true |
2186 |
1 |
|
T1 |
9 |
|
T2 |
52 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10701 |
1 |
|
T2 |
10 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
242 |
1 |
|
T2 |
6 |
|
T16 |
1 |
|
T57 |
1 |
| others[2] |
256 |
1 |
|
T2 |
12 |
|
T3 |
1 |
|
T17 |
1 |
| others[3] |
408 |
1 |
|
T2 |
15 |
|
T19 |
1 |
|
T22 |
1 |
| false |
126 |
1 |
|
T2 |
5 |
|
T27 |
1 |
|
T99 |
1 |
| true |
3315 |
1 |
|
T1 |
13 |
|
T2 |
53 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10722 |
1 |
|
T2 |
6 |
|
T4 |
1 |
|
T51 |
138 |
| others[1] |
253 |
1 |
|
T2 |
14 |
|
T3 |
1 |
|
T16 |
1 |
| others[2] |
245 |
1 |
|
T2 |
14 |
|
T22 |
1 |
|
T133 |
1 |
| others[3] |
401 |
1 |
|
T2 |
17 |
|
T96 |
1 |
|
T38 |
1 |
| false |
123 |
1 |
|
T2 |
6 |
|
T188 |
1 |
|
T99 |
1 |
| true |
3304 |
1 |
|
T1 |
13 |
|
T2 |
44 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11252 |
1 |
|
T1 |
4 |
|
T2 |
22 |
|
T3 |
1 |
| others[1] |
791 |
1 |
|
T1 |
2 |
|
T2 |
20 |
|
T15 |
1 |
| others[2] |
767 |
1 |
|
T1 |
4 |
|
T2 |
15 |
|
T22 |
1 |
| others[3] |
1297 |
1 |
|
T1 |
3 |
|
T2 |
35 |
|
T19 |
1 |
| false |
435 |
1 |
|
T2 |
9 |
|
T52 |
1 |
|
T36 |
1 |
| true |
506 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11288 |
1 |
|
T1 |
1 |
|
T2 |
25 |
|
T3 |
1 |
| others[1] |
781 |
1 |
|
T1 |
1 |
|
T2 |
27 |
|
T188 |
1 |
| others[2] |
790 |
1 |
|
T1 |
4 |
|
T2 |
11 |
|
T16 |
1 |
| others[3] |
1274 |
1 |
|
T1 |
5 |
|
T2 |
24 |
|
T22 |
1 |
| false |
399 |
1 |
|
T1 |
2 |
|
T2 |
14 |
|
T180 |
4 |
| true |
516 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2599 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
1 |
| others[1] |
2626 |
1 |
|
T1 |
3 |
|
T2 |
8 |
|
T51 |
19 |
| others[2] |
2650 |
1 |
|
T1 |
3 |
|
T2 |
13 |
|
T16 |
1 |
| others[3] |
4328 |
1 |
|
T1 |
6 |
|
T2 |
14 |
|
T51 |
54 |
| false |
1327 |
1 |
|
T2 |
2 |
|
T4 |
1 |
|
T19 |
1 |
| true |
1518 |
1 |
|
T2 |
53 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10732 |
1 |
|
T2 |
13 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
266 |
1 |
|
T2 |
3 |
|
T16 |
1 |
|
T17 |
1 |
| others[2] |
293 |
1 |
|
T2 |
14 |
|
T4 |
1 |
|
T25 |
1 |
| others[3] |
399 |
1 |
|
T2 |
16 |
|
T59 |
1 |
|
T192 |
1 |
| false |
148 |
1 |
|
T2 |
4 |
|
T23 |
1 |
|
T26 |
1 |
| true |
3210 |
1 |
|
T1 |
13 |
|
T2 |
51 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10913 |
1 |
|
T1 |
2 |
|
T2 |
6 |
|
T6 |
1 |
| others[1] |
407 |
1 |
|
T2 |
3 |
|
T25 |
1 |
|
T180 |
5 |
| others[2] |
482 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T15 |
1 |
| others[3] |
777 |
1 |
|
T1 |
2 |
|
T2 |
26 |
|
T10 |
1 |
| false |
233 |
1 |
|
T2 |
9 |
|
T96 |
1 |
|
T180 |
5 |
| true |
2236 |
1 |
|
T1 |
8 |
|
T2 |
47 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10724 |
1 |
|
T2 |
11 |
|
T4 |
1 |
|
T51 |
138 |
| others[1] |
287 |
1 |
|
T2 |
7 |
|
T37 |
1 |
|
T27 |
1 |
| others[2] |
251 |
1 |
|
T2 |
12 |
|
T3 |
1 |
|
T6 |
1 |
| others[3] |
399 |
1 |
|
T2 |
14 |
|
T22 |
1 |
|
T96 |
1 |
| false |
140 |
1 |
|
T2 |
6 |
|
T16 |
1 |
|
T19 |
1 |
| true |
3247 |
1 |
|
T1 |
13 |
|
T2 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10712 |
1 |
|
T2 |
5 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
231 |
1 |
|
T2 |
17 |
|
T19 |
1 |
|
T23 |
1 |
| others[2] |
252 |
1 |
|
T2 |
8 |
|
T22 |
1 |
|
T203 |
1 |
| others[3] |
418 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T97 |
1 |
| false |
119 |
1 |
|
T2 |
6 |
|
T133 |
1 |
|
T407 |
1 |
| true |
3316 |
1 |
|
T1 |
13 |
|
T2 |
43 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11267 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T3 |
1 |
| others[1] |
809 |
1 |
|
T1 |
4 |
|
T2 |
15 |
|
T16 |
1 |
| others[2] |
740 |
1 |
|
T1 |
1 |
|
T2 |
25 |
|
T19 |
1 |
| others[3] |
1319 |
1 |
|
T1 |
3 |
|
T2 |
32 |
|
T15 |
1 |
| false |
419 |
1 |
|
T1 |
2 |
|
T2 |
8 |
|
T36 |
1 |
| true |
494 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11288 |
1 |
|
T1 |
3 |
|
T2 |
23 |
|
T51 |
138 |
| others[1] |
813 |
1 |
|
T1 |
3 |
|
T2 |
16 |
|
T4 |
1 |
| others[2] |
802 |
1 |
|
T1 |
2 |
|
T2 |
20 |
|
T15 |
1 |
| others[3] |
1246 |
1 |
|
T1 |
4 |
|
T2 |
29 |
|
T3 |
1 |
| false |
406 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T96 |
2 |
| true |
493 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2588 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T16 |
1 |
| others[1] |
2587 |
1 |
|
T1 |
6 |
|
T2 |
9 |
|
T3 |
1 |
| others[2] |
2564 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T19 |
1 |
| others[3] |
4463 |
1 |
|
T1 |
5 |
|
T2 |
21 |
|
T4 |
1 |
| false |
1338 |
1 |
|
T2 |
6 |
|
T22 |
1 |
|
T51 |
13 |
| true |
1508 |
1 |
|
T2 |
50 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10721 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T51 |
138 |
| others[1] |
292 |
1 |
|
T2 |
14 |
|
T6 |
1 |
|
T19 |
1 |
| others[2] |
262 |
1 |
|
T2 |
11 |
|
T20 |
1 |
|
T192 |
1 |
| others[3] |
438 |
1 |
|
T2 |
18 |
|
T16 |
1 |
|
T4 |
1 |
| false |
141 |
1 |
|
T2 |
7 |
|
T21 |
1 |
|
T207 |
1 |
| true |
3194 |
1 |
|
T1 |
13 |
|
T2 |
40 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10921 |
1 |
|
T2 |
10 |
|
T121 |
1 |
|
T51 |
138 |
| others[1] |
417 |
1 |
|
T1 |
2 |
|
T2 |
7 |
|
T22 |
1 |
| others[2] |
459 |
1 |
|
T1 |
3 |
|
T2 |
12 |
|
T3 |
1 |
| others[3] |
798 |
1 |
|
T1 |
1 |
|
T2 |
15 |
|
T17 |
1 |
| false |
213 |
1 |
|
T1 |
2 |
|
T2 |
6 |
|
T4 |
1 |
| true |
2240 |
1 |
|
T1 |
5 |
|
T2 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10716 |
1 |
|
T2 |
7 |
|
T6 |
1 |
|
T51 |
138 |
| others[1] |
253 |
1 |
|
T2 |
13 |
|
T36 |
1 |
|
T32 |
1 |
| others[2] |
279 |
1 |
|
T2 |
7 |
|
T22 |
1 |
|
T23 |
1 |
| others[3] |
401 |
1 |
|
T2 |
17 |
|
T114 |
1 |
|
T190 |
1 |
| false |
119 |
1 |
|
T2 |
5 |
|
T408 |
1 |
|
T409 |
1 |
| true |
3280 |
1 |
|
T1 |
13 |
|
T2 |
52 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10702 |
1 |
|
T2 |
6 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
250 |
1 |
|
T2 |
10 |
|
T207 |
1 |
|
T27 |
1 |
| others[2] |
266 |
1 |
|
T2 |
9 |
|
T23 |
1 |
|
T36 |
1 |
| others[3] |
386 |
1 |
|
T2 |
26 |
|
T16 |
1 |
|
T37 |
1 |
| false |
121 |
1 |
|
T2 |
4 |
|
T7 |
1 |
|
T82 |
6 |
| true |
3323 |
1 |
|
T1 |
13 |
|
T2 |
46 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11262 |
1 |
|
T1 |
4 |
|
T2 |
10 |
|
T3 |
1 |
| others[1] |
757 |
1 |
|
T1 |
2 |
|
T2 |
29 |
|
T22 |
1 |
| others[2] |
789 |
1 |
|
T1 |
2 |
|
T2 |
25 |
|
T57 |
1 |
| others[3] |
1357 |
1 |
|
T1 |
4 |
|
T2 |
25 |
|
T16 |
1 |
| false |
395 |
1 |
|
T1 |
1 |
|
T2 |
12 |
|
T15 |
1 |
| true |
488 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11247 |
1 |
|
T1 |
4 |
|
T2 |
17 |
|
T3 |
1 |
| others[1] |
820 |
1 |
|
T1 |
2 |
|
T2 |
23 |
|
T4 |
1 |
| others[2] |
786 |
1 |
|
T1 |
2 |
|
T2 |
16 |
|
T96 |
1 |
| others[3] |
1277 |
1 |
|
T1 |
3 |
|
T2 |
34 |
|
T23 |
1 |
| false |
406 |
1 |
|
T1 |
2 |
|
T2 |
11 |
|
T180 |
7 |
| true |
512 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2616 |
1 |
|
T1 |
3 |
|
T2 |
3 |
|
T4 |
1 |
| others[1] |
2472 |
1 |
|
T1 |
3 |
|
T2 |
8 |
|
T51 |
19 |
| others[2] |
2689 |
1 |
|
T1 |
4 |
|
T2 |
11 |
|
T3 |
1 |
| others[3] |
4448 |
1 |
|
T1 |
2 |
|
T2 |
16 |
|
T16 |
1 |
| false |
1339 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T51 |
11 |
| true |
1484 |
1 |
|
T2 |
56 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10723 |
1 |
|
T2 |
11 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
277 |
1 |
|
T2 |
6 |
|
T16 |
1 |
|
T188 |
1 |
| others[2] |
298 |
1 |
|
T2 |
6 |
|
T57 |
1 |
|
T25 |
1 |
| others[3] |
415 |
1 |
|
T2 |
16 |
|
T53 |
1 |
|
T67 |
1 |
| false |
139 |
1 |
|
T2 |
9 |
|
T96 |
1 |
|
T37 |
1 |
| true |
3196 |
1 |
|
T1 |
13 |
|
T2 |
53 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |