Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10958 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T19 |
1 |
| others[1] |
419 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T17 |
1 |
| others[2] |
439 |
1 |
|
T2 |
9 |
|
T4 |
1 |
|
T180 |
6 |
| others[3] |
758 |
1 |
|
T1 |
4 |
|
T2 |
12 |
|
T16 |
1 |
| false |
258 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T180 |
5 |
| true |
2216 |
1 |
|
T1 |
6 |
|
T2 |
54 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10702 |
1 |
|
T2 |
4 |
|
T4 |
1 |
|
T51 |
138 |
| others[1] |
243 |
1 |
|
T2 |
12 |
|
T23 |
1 |
|
T96 |
1 |
| others[2] |
251 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T16 |
1 |
| others[3] |
434 |
1 |
|
T2 |
22 |
|
T22 |
1 |
|
T57 |
1 |
| false |
139 |
1 |
|
T2 |
6 |
|
T366 |
1 |
|
T210 |
1 |
| true |
3279 |
1 |
|
T1 |
13 |
|
T2 |
52 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10694 |
1 |
|
T2 |
4 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
243 |
1 |
|
T2 |
11 |
|
T4 |
1 |
|
T192 |
1 |
| others[2] |
241 |
1 |
|
T2 |
15 |
|
T19 |
1 |
|
T81 |
1 |
| others[3] |
410 |
1 |
|
T2 |
23 |
|
T3 |
1 |
|
T16 |
1 |
| false |
120 |
1 |
|
T2 |
8 |
|
T32 |
1 |
|
T27 |
1 |
| true |
3340 |
1 |
|
T1 |
13 |
|
T2 |
40 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11283 |
1 |
|
T1 |
4 |
|
T2 |
11 |
|
T51 |
138 |
| others[1] |
769 |
1 |
|
T1 |
4 |
|
T2 |
29 |
|
T3 |
1 |
| others[2] |
783 |
1 |
|
T1 |
2 |
|
T2 |
21 |
|
T4 |
1 |
| others[3] |
1333 |
1 |
|
T1 |
2 |
|
T2 |
35 |
|
T15 |
1 |
| false |
399 |
1 |
|
T1 |
1 |
|
T2 |
5 |
|
T180 |
8 |
| true |
481 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11279 |
1 |
|
T1 |
4 |
|
T2 |
21 |
|
T3 |
1 |
| others[1] |
814 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T16 |
1 |
| others[2] |
760 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T36 |
1 |
| others[3] |
1293 |
1 |
|
T1 |
3 |
|
T2 |
25 |
|
T22 |
1 |
| false |
397 |
1 |
|
T1 |
1 |
|
T2 |
16 |
|
T15 |
1 |
| true |
505 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2648 |
1 |
|
T1 |
5 |
|
T2 |
11 |
|
T51 |
20 |
| others[1] |
2648 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T16 |
1 |
| others[2] |
2597 |
1 |
|
T1 |
2 |
|
T2 |
18 |
|
T51 |
30 |
| others[3] |
4293 |
1 |
|
T1 |
6 |
|
T2 |
14 |
|
T4 |
1 |
| false |
1379 |
1 |
|
T2 |
6 |
|
T19 |
1 |
|
T22 |
1 |
| true |
1483 |
1 |
|
T2 |
47 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10729 |
1 |
|
T2 |
7 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
243 |
1 |
|
T2 |
6 |
|
T53 |
1 |
|
T20 |
1 |
| others[2] |
274 |
1 |
|
T2 |
14 |
|
T23 |
1 |
|
T96 |
1 |
| others[3] |
436 |
1 |
|
T2 |
13 |
|
T6 |
1 |
|
T204 |
1 |
| false |
136 |
1 |
|
T2 |
2 |
|
T19 |
1 |
|
T57 |
1 |
| true |
3230 |
1 |
|
T1 |
13 |
|
T2 |
59 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10914 |
1 |
|
T2 |
5 |
|
T17 |
1 |
|
T51 |
138 |
| others[1] |
462 |
1 |
|
T1 |
3 |
|
T2 |
10 |
|
T15 |
1 |
| others[2] |
489 |
1 |
|
T1 |
2 |
|
T2 |
8 |
|
T36 |
1 |
| others[3] |
772 |
1 |
|
T2 |
17 |
|
T3 |
1 |
|
T52 |
1 |
| false |
257 |
1 |
|
T2 |
7 |
|
T10 |
1 |
|
T79 |
1 |
| true |
2154 |
1 |
|
T1 |
8 |
|
T2 |
54 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10714 |
1 |
|
T2 |
12 |
|
T16 |
1 |
|
T51 |
138 |
| others[1] |
246 |
1 |
|
T2 |
14 |
|
T53 |
1 |
|
T37 |
1 |
| others[2] |
231 |
1 |
|
T2 |
10 |
|
T22 |
1 |
|
T396 |
1 |
| others[3] |
417 |
1 |
|
T2 |
15 |
|
T23 |
1 |
|
T59 |
1 |
| false |
128 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T188 |
1 |
| true |
3312 |
1 |
|
T1 |
13 |
|
T2 |
49 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10729 |
1 |
|
T2 |
11 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
244 |
1 |
|
T2 |
9 |
|
T26 |
1 |
|
T379 |
1 |
| others[2] |
244 |
1 |
|
T2 |
10 |
|
T188 |
1 |
|
T38 |
1 |
| others[3] |
412 |
1 |
|
T2 |
19 |
|
T17 |
1 |
|
T19 |
1 |
| false |
123 |
1 |
|
T2 |
1 |
|
T81 |
1 |
|
T99 |
1 |
| true |
3296 |
1 |
|
T1 |
13 |
|
T2 |
51 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11255 |
1 |
|
T1 |
3 |
|
T2 |
25 |
|
T51 |
138 |
| others[1] |
763 |
1 |
|
T1 |
2 |
|
T2 |
16 |
|
T4 |
1 |
| others[2] |
782 |
1 |
|
T1 |
4 |
|
T2 |
20 |
|
T22 |
1 |
| others[3] |
1331 |
1 |
|
T1 |
3 |
|
T2 |
29 |
|
T3 |
1 |
| false |
408 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T15 |
1 |
| true |
509 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11271 |
1 |
|
T2 |
23 |
|
T3 |
1 |
|
T16 |
1 |
| others[1] |
794 |
1 |
|
T1 |
2 |
|
T2 |
24 |
|
T121 |
1 |
| others[2] |
762 |
1 |
|
T1 |
4 |
|
T2 |
10 |
|
T10 |
1 |
| others[3] |
1268 |
1 |
|
T1 |
5 |
|
T2 |
35 |
|
T15 |
1 |
| false |
442 |
1 |
|
T1 |
2 |
|
T2 |
9 |
|
T22 |
1 |
| true |
511 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2621 |
1 |
|
T1 |
2 |
|
T2 |
9 |
|
T4 |
1 |
| others[1] |
2616 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T16 |
1 |
| others[2] |
2652 |
1 |
|
T1 |
4 |
|
T2 |
12 |
|
T51 |
23 |
| others[3] |
4270 |
1 |
|
T1 |
4 |
|
T2 |
14 |
|
T19 |
1 |
| false |
1381 |
1 |
|
T1 |
3 |
|
T2 |
5 |
|
T51 |
19 |
| true |
1508 |
1 |
|
T2 |
50 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10719 |
1 |
|
T2 |
9 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
267 |
1 |
|
T2 |
9 |
|
T188 |
1 |
|
T114 |
1 |
| others[2] |
285 |
1 |
|
T2 |
10 |
|
T96 |
1 |
|
T97 |
1 |
| others[3] |
462 |
1 |
|
T2 |
21 |
|
T3 |
1 |
|
T17 |
1 |
| false |
135 |
1 |
|
T2 |
4 |
|
T23 |
1 |
|
T53 |
1 |
| true |
3180 |
1 |
|
T1 |
13 |
|
T2 |
48 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10940 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T17 |
1 |
| others[1] |
468 |
1 |
|
T1 |
4 |
|
T2 |
14 |
|
T15 |
1 |
| others[2] |
501 |
1 |
|
T2 |
9 |
|
T4 |
1 |
|
T96 |
1 |
| others[3] |
734 |
1 |
|
T1 |
2 |
|
T2 |
8 |
|
T3 |
1 |
| false |
244 |
1 |
|
T1 |
2 |
|
T2 |
6 |
|
T20 |
1 |
| true |
2161 |
1 |
|
T1 |
4 |
|
T2 |
56 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10719 |
1 |
|
T2 |
13 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
263 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T53 |
1 |
| others[2] |
288 |
1 |
|
T2 |
12 |
|
T23 |
1 |
|
T36 |
1 |
| others[3] |
386 |
1 |
|
T2 |
15 |
|
T57 |
1 |
|
T113 |
1 |
| false |
127 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T49 |
1 |
| true |
3265 |
1 |
|
T1 |
13 |
|
T2 |
52 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10712 |
1 |
|
T2 |
7 |
|
T22 |
1 |
|
T51 |
138 |
| others[1] |
248 |
1 |
|
T2 |
12 |
|
T23 |
1 |
|
T213 |
1 |
| others[2] |
226 |
1 |
|
T2 |
10 |
|
T53 |
1 |
|
T38 |
1 |
| others[3] |
412 |
1 |
|
T2 |
19 |
|
T36 |
1 |
|
T37 |
1 |
| false |
124 |
1 |
|
T2 |
4 |
|
T17 |
1 |
|
T207 |
1 |
| true |
3326 |
1 |
|
T1 |
13 |
|
T2 |
49 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11241 |
1 |
|
T1 |
2 |
|
T2 |
22 |
|
T4 |
1 |
| others[1] |
761 |
1 |
|
T1 |
3 |
|
T2 |
21 |
|
T96 |
1 |
| others[2] |
808 |
1 |
|
T1 |
3 |
|
T2 |
22 |
|
T3 |
1 |
| others[3] |
1342 |
1 |
|
T1 |
5 |
|
T2 |
30 |
|
T53 |
1 |
| false |
409 |
1 |
|
T2 |
6 |
|
T15 |
1 |
|
T23 |
1 |
| true |
487 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11255 |
1 |
|
T1 |
2 |
|
T2 |
14 |
|
T51 |
138 |
| others[1] |
792 |
1 |
|
T1 |
4 |
|
T2 |
13 |
|
T16 |
1 |
| others[2] |
797 |
1 |
|
T1 |
2 |
|
T2 |
19 |
|
T4 |
1 |
| others[3] |
1288 |
1 |
|
T1 |
3 |
|
T2 |
45 |
|
T3 |
1 |
| false |
398 |
1 |
|
T1 |
2 |
|
T2 |
10 |
|
T180 |
7 |
| true |
518 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2573 |
1 |
|
T1 |
3 |
|
T2 |
11 |
|
T51 |
27 |
| others[1] |
2618 |
1 |
|
T1 |
2 |
|
T2 |
8 |
|
T3 |
1 |
| others[2] |
2648 |
1 |
|
T1 |
4 |
|
T2 |
12 |
|
T16 |
1 |
| others[3] |
4358 |
1 |
|
T1 |
3 |
|
T2 |
14 |
|
T19 |
1 |
| false |
1322 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T51 |
20 |
| true |
1529 |
1 |
|
T2 |
52 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10756 |
1 |
|
T2 |
13 |
|
T6 |
1 |
|
T51 |
138 |
| others[1] |
274 |
1 |
|
T2 |
11 |
|
T4 |
1 |
|
T22 |
1 |
| others[2] |
254 |
1 |
|
T2 |
11 |
|
T3 |
1 |
|
T188 |
1 |
| others[3] |
428 |
1 |
|
T2 |
20 |
|
T23 |
1 |
|
T36 |
1 |
| false |
144 |
1 |
|
T2 |
5 |
|
T177 |
1 |
|
T24 |
1 |
| true |
3192 |
1 |
|
T1 |
13 |
|
T2 |
41 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10893 |
1 |
|
T2 |
10 |
|
T10 |
1 |
|
T51 |
138 |
| others[1] |
412 |
1 |
|
T2 |
11 |
|
T11 |
1 |
|
T188 |
1 |
| others[2] |
463 |
1 |
|
T1 |
2 |
|
T2 |
6 |
|
T16 |
1 |
| others[3] |
773 |
1 |
|
T1 |
2 |
|
T2 |
12 |
|
T15 |
1 |
| false |
235 |
1 |
|
T1 |
2 |
|
T2 |
3 |
|
T5 |
1 |
| true |
2272 |
1 |
|
T1 |
7 |
|
T2 |
59 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10727 |
1 |
|
T2 |
12 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
233 |
1 |
|
T2 |
11 |
|
T4 |
1 |
|
T32 |
1 |
| others[2] |
261 |
1 |
|
T2 |
13 |
|
T3 |
1 |
|
T23 |
1 |
| others[3] |
424 |
1 |
|
T2 |
15 |
|
T6 |
1 |
|
T22 |
1 |
| false |
130 |
1 |
|
T2 |
5 |
|
T177 |
1 |
|
T34 |
1 |
| true |
3273 |
1 |
|
T1 |
13 |
|
T2 |
45 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10725 |
1 |
|
T2 |
10 |
|
T17 |
1 |
|
T51 |
138 |
| others[1] |
239 |
1 |
|
T2 |
8 |
|
T53 |
1 |
|
T89 |
1 |
| others[2] |
229 |
1 |
|
T2 |
12 |
|
T16 |
1 |
|
T36 |
1 |
| others[3] |
385 |
1 |
|
T2 |
15 |
|
T96 |
1 |
|
T207 |
1 |
| false |
119 |
1 |
|
T2 |
3 |
|
T19 |
1 |
|
T96 |
1 |
| true |
3351 |
1 |
|
T1 |
13 |
|
T2 |
53 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11243 |
1 |
|
T2 |
16 |
|
T51 |
138 |
|
T18 |
247 |
| others[1] |
771 |
1 |
|
T1 |
5 |
|
T2 |
23 |
|
T3 |
1 |
| others[2] |
823 |
1 |
|
T1 |
4 |
|
T2 |
19 |
|
T19 |
1 |
| others[3] |
1337 |
1 |
|
T1 |
3 |
|
T2 |
31 |
|
T4 |
1 |
| false |
396 |
1 |
|
T1 |
1 |
|
T2 |
12 |
|
T22 |
1 |
| true |
478 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |