Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	2	14	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	2	14	87.50	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	230675	1		T1	8		T2	100		T3	1318
auto[FlashEraseBank]	234515	1		T1	5		T2	1042		T3	900

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	259255	1		T1	2		T2	582		T3	1231
auto[FlashOpProgram]	184688	1		T1	7		T2	510		T3	987
auto[FlashOpErase]	17247	1		T1	4		T2	50		T15	4
auto[FlashOpInvalid]	4000	1		T94	200		T41	200		T98	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	259255	1		T1	2		T2	582		T3	1231
op[FlashOpProgram]	184688	1		T1	7		T2	510		T3	987
op[FlashOpErase]	17247	1		T1	4		T2	50		T15	4
read_erase_read	710	1		T1	1		T2	9		T15	2
read_prog_read	1328	1		T2	3		T3	2		T15	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	321015	1		T1	13		T2	97		T3	1990
auto[FlashPartInfo]	140389	1		T2	1044		T3	207		T16	257
auto[FlashPartInfo1]	799	1		T3	5		T4	3		T17	1
auto[FlashPartInfo2]	2987	1		T2	1		T3	16		T16	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpErase] , auto[FlashOpInvalid]]	--	--	2

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	193315	1		T1	2		T2	37		T3	1216
auto[FlashPartData]	auto[FlashOpProgram]	119994	1		T1	7		T2	28		T3	774
auto[FlashPartData]	auto[FlashOpErase]	3776	1		T1	4		T2	32		T15	4
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T94	196		T41	196		T98	192
auto[FlashPartInfo]	auto[FlashOpRead]	63510	1		T2	545		T6	272		T5	1
auto[FlashPartInfo]	auto[FlashOpProgram]	63378	1		T2	481		T3	207		T16	257
auto[FlashPartInfo]	auto[FlashOpErase]	13443	1		T2	18		T79	1		T51	213
auto[FlashPartInfo]	auto[FlashOpInvalid]	58	1		T94	4		T41	4		T98	8
auto[FlashPartInfo1]	auto[FlashOpRead]	670	1		T3	5		T4	3		T17	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	129	1		T80	32		T106	32		T84	32
auto[FlashPartInfo2]	auto[FlashOpRead]	1760	1		T3	10		T4	1		T17	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	1187	1		T2	1		T3	6		T16	4
auto[FlashPartInfo2]	auto[FlashOpErase]	28	1		T40	1		T105	1		T116	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T118	2		T328	2		T329	2