Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33190	1		T1	9		T2	8		T15	32
auto[1]	174	1		T406	113		T408	18		T412	2
auto[2]	180	1		T101	29		T413	1		T102	8
auto[3]	299	1		T24	2		T93	1		T303	39

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8478	1		T1	2		T2	2		T15	8
evic_idx[1]	8475	1		T1	3		T2	2		T15	8
evic_idx[2]	8460	1		T1	2		T2	2		T15	8
evic_idx[3]	8430	1		T1	2		T2	2		T15	8

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32724	1		T15	16		T51	404		T18	764
evic_op[2]	551	1		T1	1		T15	16		T52	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8070	1		T15	4		T51	101		T18	191
evic_idx[0]	evic_op[1]	auto[1]	46	1		T406	35		T408	2		T414	9
evic_idx[0]	evic_op[1]	auto[2]	4	1		T275	4		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	86	1		T303	8		T408	21		T243	2
evic_idx[0]	evic_op[2]	auto[0]	82	1		T15	4		T52	4		T113	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T415	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	36	1		T101	9		T209	2		T416	9
evic_idx[0]	evic_op[2]	auto[3]	11	1		T93	1		T388	1		T417	1
evic_idx[1]	evic_op[1]	auto[0]	8081	1		T15	4		T51	101		T18	191
evic_idx[1]	evic_op[1]	auto[1]	48	1		T406	32		T408	5		T414	11
evic_idx[1]	evic_op[1]	auto[2]	1	1		T275	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	64	1		T303	10		T408	9		T243	2
evic_idx[1]	evic_op[2]	auto[0]	89	1		T1	1		T15	4		T52	4
evic_idx[1]	evic_op[2]	auto[1]	6	1		T412	1		T418	1		T419	1
evic_idx[1]	evic_op[2]	auto[2]	34	1		T101	4		T209	3		T416	13
evic_idx[1]	evic_op[2]	auto[3]	10	1		T24	1		T420	1		T421	1
evic_idx[2]	evic_op[1]	auto[0]	8074	1		T15	4		T51	101		T18	191
evic_idx[2]	evic_op[1]	auto[1]	40	1		T406	26		T408	6		T422	3
evic_idx[2]	evic_op[1]	auto[2]	4	1		T275	4		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	53	1		T303	10		T408	6		T243	4
evic_idx[2]	evic_op[2]	auto[0]	82	1		T15	4		T52	4		T183	1
evic_idx[2]	evic_op[2]	auto[1]	2	1		T412	1		T415	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	47	1		T101	5		T413	1		T209	5
evic_idx[2]	evic_op[2]	auto[3]	16	1		T24	1		T35	1		T100	1
evic_idx[3]	evic_op[1]	auto[0]	8072	1		T15	4		T51	101		T18	191
evic_idx[3]	evic_op[1]	auto[1]	30	1		T406	20		T408	5		T422	1
evic_idx[3]	evic_op[1]	auto[2]	1	1		T275	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	50	1		T303	11		T408	7		T243	5
evic_idx[3]	evic_op[2]	auto[0]	88	1		T15	4		T52	4		T183	1
evic_idx[3]	evic_op[2]	auto[1]	1	1		T415	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	37	1		T101	11		T209	5		T416	11
evic_idx[3]	evic_op[2]	auto[3]	9	1		T423	1		T424	1		T425	1