Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	40186	1		T317	9780		T318	8191		T319	1630
rd_lvl[2]	49113	1		T59	1878		T204	1775		T274	1561
rd_lvl[3]	14643	1		T59	1644		T204	1334		T320	1227
rd_lvl[4]	18223	1		T59	546		T204	385		T320	2471
rd_lvl[5]	15961	1		T59	1367		T204	1063		T272	1641
rd_lvl[6]	14889	1		T59	1846		T204	1349		T272	523
rd_lvl[7]	8314	1		T204	39		T214	171		T320	163
rd_lvl[8]	12813	1		T204	39		T130	1091		T321	51
rd_lvl[9]	8423	1		T22	627		T204	39		T130	385
rd_lvl[10]	5332	1		T22	277		T59	1		T31	527
rd_lvl[11]	6905	1		T23	488		T59	1		T67	552
rd_lvl[12]	8552	1		T6	544		T22	2		T23	198
rd_lvl[13]	7860	1		T6	420		T59	60		T204	35
rd_lvl[14]	5482	1		T6	1		T322	464		T323	38
rd_lvl[15]	3999	1		T6	38		T322	323		T324	143