Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	340434	1		T1	2		T2	2		T3	2
all_pins[1]	340434	1		T1	2		T2	2		T3	2
all_pins[2]	340434	1		T1	2		T2	2		T3	2
all_pins[3]	340434	1		T1	2		T2	2		T3	2
all_pins[4]	340434	1		T1	2		T2	2		T3	2
all_pins[5]	340434	1		T1	2		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1718627	1		T1	12		T2	12		T3	12
values[0x1]	323977	1		T6	2006		T22	1812		T23	1372
transitions[0x0=>0x1]	296904	1		T6	2006		T22	1812		T23	1372
transitions[0x1=>0x0]	296891	1		T6	2006		T22	1812		T23	1372

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	340288	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	146	1		T259	2		T260	1		T261	7
all_pins[0]	transitions[0x0=>0x1]	69	1		T259	1		T260	1		T261	5
all_pins[0]	transitions[0x1=>0x0]	79	1		T259	2		T260	3		T261	1
all_pins[1]	values[0x0]	340278	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	156	1		T259	3		T260	3		T261	3
all_pins[1]	transitions[0x0=>0x1]	123	1		T259	1		T260	2		T261	3
all_pins[1]	transitions[0x1=>0x0]	1464	1		T330	539		T331	247		T332	346
all_pins[2]	values[0x0]	338937	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	1497	1		T330	539		T331	247		T332	346
all_pins[2]	transitions[0x0=>0x1]	49	1		T259	2		T260	2		T313	1
all_pins[2]	transitions[0x1=>0x0]	220774	1		T6	1003		T22	906		T23	686
all_pins[3]	values[0x0]	118212	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	222222	1		T6	1003		T22	906		T23	686
all_pins[3]	transitions[0x0=>0x1]	196772	1		T6	1003		T22	906		T23	686
all_pins[3]	transitions[0x1=>0x0]	74432	1		T6	1003		T22	906		T23	686
all_pins[4]	values[0x0]	240552	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	99882	1		T6	1003		T22	906		T23	686
all_pins[4]	transitions[0x0=>0x1]	99862	1		T6	1003		T22	906		T23	686
all_pins[4]	transitions[0x1=>0x0]	54	1		T259	1		T261	3		T313	1
all_pins[5]	values[0x0]	340360	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	74	1		T259	1		T260	1		T261	4
all_pins[5]	transitions[0x0=>0x1]	29	1		T261	1		T313	2		T314	1
all_pins[5]	transitions[0x1=>0x0]	88	1		T259	2		T261	3		T312	2