Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 272 1 T259 4 T260 4 T261 7
all_values[1] 272 1 T259 4 T260 4 T261 7
all_values[2] 272 1 T259 4 T260 4 T261 7
all_values[3] 272 1 T259 4 T260 4 T261 7
all_values[4] 272 1 T259 4 T260 4 T261 7
all_values[5] 272 1 T259 4 T260 4 T261 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 910 1 T259 11 T260 13 T261 24
auto[1] 722 1 T259 13 T260 11 T261 18



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 536 1 T259 10 T260 7 T261 12
auto[1] 1096 1 T259 14 T260 17 T261 30



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 959 1 T259 16 T260 14 T261 22
auto[1] 673 1 T259 8 T260 10 T261 20



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intr   cp_intr_test   cp_intr_en   cp_intr_state   COUNT   AT LEAST   NUMBER   
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intr   cp_intr_test   cp_intr_en   cp_intr_state   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] auto[1] 92 1 T259 2 T260 2 T261 1
all_values[0] auto[0] auto[1] auto[1] 71 1 T259 2 T261 4 T312 1
all_values[0] auto[1] auto[0] auto[1] 63 1 T260 2 T261 1 T312 1
all_values[0] auto[1] auto[1] auto[1] 46 1 T261 1 T312 1 T313 1
all_values[1] auto[0] auto[0] auto[1] 89 1 T259 1 T260 3 T261 3
all_values[1] auto[0] auto[1] auto[1] 68 1 T259 1 T260 1 T261 1
all_values[1] auto[1] auto[0] auto[1] 60 1 T259 1 T261 3 T312 1
all_values[1] auto[1] auto[1] auto[1] 55 1 T259 1 T312 2 T313 1
all_values[2] auto[0] auto[0] auto[0] 91 1 T261 1 T312 3 T313 2
all_values[2] auto[0] auto[1] auto[0] 62 1 T259 2 T260 1 T261 1
all_values[2] auto[1] auto[0] auto[1] 62 1 T259 1 T260 1 T261 5
all_values[2] auto[1] auto[1] auto[1] 57 1 T259 1 T260 2 T312 1
all_values[3] auto[0] auto[0] auto[0] 99 1 T259 1 T260 1 T312 3
all_values[3] auto[0] auto[1] auto[0] 70 1 T259 2 T260 2 T261 2
all_values[3] auto[1] auto[0] auto[1] 60 1 T259 1 T261 1 T313 2
all_values[3] auto[1] auto[1] auto[1] 43 1 T260 1 T261 4 T312 1
all_values[4] auto[0] auto[0] auto[0] 68 1 T259 2 T260 1 T261 5
all_values[4] auto[0] auto[0] auto[1] 22 1 T260 1 T313 1 T314 1
all_values[4] auto[0] auto[1] auto[0] 41 1 T259 1 T261 1 T315 2
all_values[4] auto[0] auto[1] auto[1] 25 1 T312 1 T314 1 T316 1
all_values[4] auto[1] auto[0] auto[1] 57 1 T312 2 T313 2 T314 2
all_values[4] auto[1] auto[1] auto[1] 59 1 T259 1 T260 2 T261 1
all_values[5] auto[0] auto[0] auto[0] 59 1 T259 1 T260 1 T261 2
all_values[5] auto[0] auto[0] auto[1] 24 1 T312 2 T313 2 T314 1
all_values[5] auto[0] auto[1] auto[0] 46 1 T259 1 T260 1 T315 2
all_values[5] auto[0] auto[1] auto[1] 32 1 T261 1 T313 2 T314 1
all_values[5] auto[1] auto[0] auto[1] 64 1 T259 1 T260 1 T261 2
all_values[5] auto[1] auto[1] auto[1] 47 1 T259 1 T260 1 T261 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal