| T1071 |
/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2242263942 |
|
|
Mar 03 02:11:58 PM PST 24 |
Mar 03 02:12:12 PM PST 24 |
108124200 ps |
| T1072 |
/workspace/coverage/default/7.flash_ctrl_invalid_op.1126811752 |
|
|
Mar 03 02:11:55 PM PST 24 |
Mar 03 02:13:02 PM PST 24 |
12208523000 ps |
| T1073 |
/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.4291027676 |
|
|
Mar 03 02:13:44 PM PST 24 |
Mar 03 02:13:58 PM PST 24 |
15358600 ps |
| T1074 |
/workspace/coverage/default/9.flash_ctrl_prog_reset.184370034 |
|
|
Mar 03 02:12:30 PM PST 24 |
Mar 03 02:12:45 PM PST 24 |
18164700 ps |
| T1075 |
/workspace/coverage/default/4.flash_ctrl_connect.737226894 |
|
|
Mar 03 02:11:14 PM PST 24 |
Mar 03 02:11:30 PM PST 24 |
15607500 ps |
| T1076 |
/workspace/coverage/default/2.flash_ctrl_stress_all.267097831 |
|
|
Mar 03 02:11:04 PM PST 24 |
Mar 03 02:22:19 PM PST 24 |
549229300 ps |
| T88 |
/workspace/coverage/default/8.flash_ctrl_mp_regions.4086115460 |
|
|
Mar 03 02:12:13 PM PST 24 |
Mar 03 02:21:55 PM PST 24 |
8678174400 ps |
| T1077 |
/workspace/coverage/default/5.flash_ctrl_rw_derr.214584090 |
|
|
Mar 03 02:11:28 PM PST 24 |
Mar 03 02:21:13 PM PST 24 |
2831828100 ps |
| T1078 |
/workspace/coverage/default/3.flash_ctrl_rw_derr.1565595692 |
|
|
Mar 03 02:11:06 PM PST 24 |
Mar 03 02:22:15 PM PST 24 |
19604922800 ps |
| T1079 |
/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.3107984694 |
|
|
Mar 03 02:14:17 PM PST 24 |
Mar 03 02:14:48 PM PST 24 |
39479400 ps |
| T1080 |
/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.763668338 |
|
|
Mar 03 02:12:07 PM PST 24 |
Mar 03 02:25:12 PM PST 24 |
110155531200 ps |
| T1081 |
/workspace/coverage/default/23.flash_ctrl_sec_info_access.945741845 |
|
|
Mar 03 02:14:48 PM PST 24 |
Mar 03 02:16:05 PM PST 24 |
6032552400 ps |
| T1082 |
/workspace/coverage/default/3.flash_ctrl_rw_serr.294924620 |
|
|
Mar 03 02:11:07 PM PST 24 |
Mar 03 02:20:16 PM PST 24 |
6910988300 ps |
| T1083 |
/workspace/coverage/default/34.flash_ctrl_alert_test.1770762218 |
|
|
Mar 03 02:15:42 PM PST 24 |
Mar 03 02:15:56 PM PST 24 |
30687300 ps |
| T1084 |
/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.684379173 |
|
|
Mar 03 02:11:00 PM PST 24 |
Mar 03 02:11:15 PM PST 24 |
25438200 ps |
| T1085 |
/workspace/coverage/default/1.flash_ctrl_serr_counter.1137729104 |
|
|
Mar 03 02:10:41 PM PST 24 |
Mar 03 02:11:32 PM PST 24 |
719325900 ps |
| T1086 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.1598022415 |
|
|
Mar 03 02:10:48 PM PST 24 |
Mar 03 02:11:20 PM PST 24 |
228302900 ps |
| T1087 |
/workspace/coverage/default/49.flash_ctrl_disable.679446191 |
|
|
Mar 03 02:16:37 PM PST 24 |
Mar 03 02:16:58 PM PST 24 |
35949800 ps |
| T1088 |
/workspace/coverage/default/41.flash_ctrl_smoke.1698271756 |
|
|
Mar 03 02:16:10 PM PST 24 |
Mar 03 02:17:03 PM PST 24 |
277035700 ps |
| T1089 |
/workspace/coverage/default/12.flash_ctrl_rw_evict.692113791 |
|
|
Mar 03 02:13:05 PM PST 24 |
Mar 03 02:13:37 PM PST 24 |
54551400 ps |
| T1090 |
/workspace/coverage/default/7.flash_ctrl_rw.3221416944 |
|
|
Mar 03 02:11:54 PM PST 24 |
Mar 03 02:20:26 PM PST 24 |
4673218600 ps |
| T1091 |
/workspace/coverage/default/17.flash_ctrl_phy_arb.3638235934 |
|
|
Mar 03 02:13:49 PM PST 24 |
Mar 03 02:20:30 PM PST 24 |
1394260500 ps |
| T1092 |
/workspace/coverage/default/13.flash_ctrl_phy_arb.564972337 |
|
|
Mar 03 02:13:07 PM PST 24 |
Mar 03 02:15:31 PM PST 24 |
154526700 ps |
| T1093 |
/workspace/coverage/default/76.flash_ctrl_connect.410903686 |
|
|
Mar 03 02:16:57 PM PST 24 |
Mar 03 02:17:10 PM PST 24 |
17313000 ps |
| T1094 |
/workspace/coverage/default/7.flash_ctrl_mp_regions.1895109432 |
|
|
Mar 03 02:11:57 PM PST 24 |
Mar 03 02:18:48 PM PST 24 |
5556496200 ps |
| T1095 |
/workspace/coverage/default/19.flash_ctrl_phy_arb.3132912449 |
|
|
Mar 03 02:14:16 PM PST 24 |
Mar 03 02:18:43 PM PST 24 |
1247893100 ps |
| T1096 |
/workspace/coverage/default/52.flash_ctrl_connect.3766860922 |
|
|
Mar 03 02:16:39 PM PST 24 |
Mar 03 02:16:56 PM PST 24 |
22976500 ps |
| T1097 |
/workspace/coverage/default/2.flash_ctrl_config_regwen.3122185854 |
|
|
Mar 03 02:11:06 PM PST 24 |
Mar 03 02:11:20 PM PST 24 |
70642200 ps |
| T1098 |
/workspace/coverage/default/12.flash_ctrl_disable.997549984 |
|
|
Mar 03 02:13:07 PM PST 24 |
Mar 03 02:13:29 PM PST 24 |
19847800 ps |
| T1099 |
/workspace/coverage/default/9.flash_ctrl_mp_regions.2074322382 |
|
|
Mar 03 02:12:24 PM PST 24 |
Mar 03 02:14:40 PM PST 24 |
5794287200 ps |
| T1100 |
/workspace/coverage/default/33.flash_ctrl_connect.4182600731 |
|
|
Mar 03 02:15:42 PM PST 24 |
Mar 03 02:15:58 PM PST 24 |
20563400 ps |
| T1101 |
/workspace/coverage/default/28.flash_ctrl_intr_rd.2538718112 |
|
|
Mar 03 02:15:13 PM PST 24 |
Mar 03 02:17:40 PM PST 24 |
1323852200 ps |
| T1102 |
/workspace/coverage/default/8.flash_ctrl_intr_rd.231387388 |
|
|
Mar 03 02:12:07 PM PST 24 |
Mar 03 02:15:05 PM PST 24 |
2583375000 ps |
| T1103 |
/workspace/coverage/default/15.flash_ctrl_mp_regions.4168092986 |
|
|
Mar 03 02:13:31 PM PST 24 |
Mar 03 02:15:46 PM PST 24 |
6491023500 ps |
| T1104 |
/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2446356066 |
|
|
Mar 03 02:10:50 PM PST 24 |
Mar 03 02:11:04 PM PST 24 |
21578200 ps |
| T1105 |
/workspace/coverage/default/77.flash_ctrl_connect.1184182695 |
|
|
Mar 03 02:16:54 PM PST 24 |
Mar 03 02:17:08 PM PST 24 |
14296100 ps |
| T1106 |
/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1215937744 |
|
|
Mar 03 02:13:25 PM PST 24 |
Mar 03 02:18:31 PM PST 24 |
34035465600 ps |
| T1107 |
/workspace/coverage/default/33.flash_ctrl_disable.1062712303 |
|
|
Mar 03 02:15:42 PM PST 24 |
Mar 03 02:16:04 PM PST 24 |
31562900 ps |
| T1108 |
/workspace/coverage/default/7.flash_ctrl_rw_evict.3907741980 |
|
|
Mar 03 02:12:01 PM PST 24 |
Mar 03 02:12:33 PM PST 24 |
67850400 ps |
| T1109 |
/workspace/coverage/default/3.flash_ctrl_error_prog_win.2220928723 |
|
|
Mar 03 02:11:10 PM PST 24 |
Mar 03 02:23:16 PM PST 24 |
1406218200 ps |
| T1110 |
/workspace/coverage/default/0.flash_ctrl_rd_intg.1978403449 |
|
|
Mar 03 02:10:43 PM PST 24 |
Mar 03 02:11:14 PM PST 24 |
127377900 ps |
| T1111 |
/workspace/coverage/default/4.flash_ctrl_stress_all.1912827008 |
|
|
Mar 03 02:11:12 PM PST 24 |
Mar 03 02:17:10 PM PST 24 |
120316200 ps |
| T1112 |
/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.796181706 |
|
|
Mar 03 02:16:00 PM PST 24 |
Mar 03 02:16:32 PM PST 24 |
103558300 ps |
| T1113 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3337711006 |
|
|
Mar 03 02:13:39 PM PST 24 |
Mar 03 02:14:08 PM PST 24 |
84411800 ps |
| T1114 |
/workspace/coverage/default/4.flash_ctrl_intr_rd.2529108026 |
|
|
Mar 03 02:11:13 PM PST 24 |
Mar 03 02:14:37 PM PST 24 |
1120775000 ps |
| T1115 |
/workspace/coverage/default/38.flash_ctrl_sec_info_access.960530560 |
|
|
Mar 03 02:16:01 PM PST 24 |
Mar 03 02:17:17 PM PST 24 |
2080377100 ps |
| T137 |
/workspace/coverage/default/3.flash_ctrl_mid_op_rst.4199532587 |
|
|
Mar 03 02:11:05 PM PST 24 |
Mar 03 02:12:14 PM PST 24 |
825712000 ps |
| T1116 |
/workspace/coverage/default/31.flash_ctrl_otp_reset.3808240661 |
|
|
Mar 03 02:15:25 PM PST 24 |
Mar 03 02:17:41 PM PST 24 |
76519500 ps |
| T1117 |
/workspace/coverage/default/0.flash_ctrl_rw.1947877441 |
|
|
Mar 03 02:10:37 PM PST 24 |
Mar 03 02:19:39 PM PST 24 |
22071292000 ps |
| T1118 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.1225651220 |
|
|
Mar 03 02:10:49 PM PST 24 |
Mar 03 02:12:11 PM PST 24 |
3302318700 ps |
| T1119 |
/workspace/coverage/default/16.flash_ctrl_connect.1178023797 |
|
|
Mar 03 02:13:49 PM PST 24 |
Mar 03 02:14:03 PM PST 24 |
21873700 ps |
| T1120 |
/workspace/coverage/default/39.flash_ctrl_alert_test.3372453161 |
|
|
Mar 03 02:16:01 PM PST 24 |
Mar 03 02:16:15 PM PST 24 |
206237000 ps |
| T1121 |
/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2394038574 |
|
|
Mar 03 02:15:25 PM PST 24 |
Mar 03 02:15:58 PM PST 24 |
37492000 ps |
| T1122 |
/workspace/coverage/default/9.flash_ctrl_fetch_code.3694404926 |
|
|
Mar 03 02:12:21 PM PST 24 |
Mar 03 02:12:42 PM PST 24 |
143710700 ps |
| T220 |
/workspace/coverage/default/40.flash_ctrl_disable.3732054964 |
|
|
Mar 03 02:16:11 PM PST 24 |
Mar 03 02:16:32 PM PST 24 |
10561400 ps |
| T1123 |
/workspace/coverage/default/3.flash_ctrl_rw.2975423795 |
|
|
Mar 03 02:11:06 PM PST 24 |
Mar 03 02:19:33 PM PST 24 |
4899910500 ps |
| T1124 |
/workspace/coverage/default/6.flash_ctrl_error_prog_win.3297631185 |
|
|
Mar 03 02:11:42 PM PST 24 |
Mar 03 02:28:20 PM PST 24 |
2514490700 ps |
| T1125 |
/workspace/coverage/default/9.flash_ctrl_phy_arb.2408858 |
|
|
Mar 03 02:12:23 PM PST 24 |
Mar 03 02:23:02 PM PST 24 |
4994547900 ps |
| T1126 |
/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.1446297972 |
|
|
Mar 03 02:15:47 PM PST 24 |
Mar 03 02:16:19 PM PST 24 |
31510500 ps |
| T1127 |
/workspace/coverage/default/23.flash_ctrl_alert_test.2796259040 |
|
|
Mar 03 02:14:50 PM PST 24 |
Mar 03 02:15:04 PM PST 24 |
218795600 ps |
| T259 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.365220450 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:16 PM PST 24 |
26444100 ps |
| T260 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2524401522 |
|
|
Mar 03 01:09:12 PM PST 24 |
Mar 03 01:09:26 PM PST 24 |
206395400 ps |
| T193 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1995042543 |
|
|
Mar 03 01:07:43 PM PST 24 |
Mar 03 01:08:04 PM PST 24 |
206691700 ps |
| T194 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1717611281 |
|
|
Mar 03 01:08:01 PM PST 24 |
Mar 03 01:08:18 PM PST 24 |
62380800 ps |
| T1128 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1809948325 |
|
|
Mar 03 01:08:54 PM PST 24 |
Mar 03 01:09:08 PM PST 24 |
23060000 ps |
| T1129 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4144470633 |
|
|
Mar 03 01:08:40 PM PST 24 |
Mar 03 01:08:56 PM PST 24 |
18187000 ps |
| T54 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1061088100 |
|
|
Mar 03 01:08:00 PM PST 24 |
Mar 03 01:08:22 PM PST 24 |
1710329200 ps |
| T195 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.149092245 |
|
|
Mar 03 01:08:39 PM PST 24 |
Mar 03 01:08:59 PM PST 24 |
58195300 ps |
| T55 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.614188210 |
|
|
Mar 03 01:08:39 PM PST 24 |
Mar 03 01:09:08 PM PST 24 |
128723800 ps |
| T56 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1451264484 |
|
|
Mar 03 01:08:51 PM PST 24 |
Mar 03 01:09:11 PM PST 24 |
208319100 ps |
| T261 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1489557994 |
|
|
Mar 03 01:09:04 PM PST 24 |
Mar 03 01:09:17 PM PST 24 |
31473500 ps |
| T1130 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.448774653 |
|
|
Mar 03 01:08:27 PM PST 24 |
Mar 03 01:08:41 PM PST 24 |
28671600 ps |
| T196 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3952875184 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:11 PM PST 24 |
157211000 ps |
| T1131 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1647783295 |
|
|
Mar 03 01:07:52 PM PST 24 |
Mar 03 01:08:07 PM PST 24 |
20644500 ps |
| T198 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1527578751 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:08:31 PM PST 24 |
139297000 ps |
| T197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2837695182 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:11 PM PST 24 |
50001600 ps |
| T312 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2294527290 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:17 PM PST 24 |
29261700 ps |
| T228 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2646879852 |
|
|
Mar 03 01:08:14 PM PST 24 |
Mar 03 01:08:29 PM PST 24 |
96635400 ps |
| T249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3659787051 |
|
|
Mar 03 01:07:43 PM PST 24 |
Mar 03 01:07:59 PM PST 24 |
118065600 ps |
| T1132 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1778389147 |
|
|
Mar 03 01:08:48 PM PST 24 |
Mar 03 01:09:02 PM PST 24 |
38924100 ps |
| T250 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1249518432 |
|
|
Mar 03 01:08:14 PM PST 24 |
Mar 03 01:08:30 PM PST 24 |
64141900 ps |
| T215 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3585132954 |
|
|
Mar 03 01:08:01 PM PST 24 |
Mar 03 01:15:34 PM PST 24 |
718577600 ps |
| T251 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.125514049 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:07:59 PM PST 24 |
99478700 ps |
| T287 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3988001331 |
|
|
Mar 03 01:08:48 PM PST 24 |
Mar 03 01:09:04 PM PST 24 |
158453600 ps |
| T313 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1431599412 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:08:21 PM PST 24 |
26885000 ps |
| T232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3722500493 |
|
|
Mar 03 01:07:46 PM PST 24 |
Mar 03 01:08:00 PM PST 24 |
56987100 ps |
| T343 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1663300054 |
|
|
Mar 03 01:08:22 PM PST 24 |
Mar 03 01:08:37 PM PST 24 |
102663200 ps |
| T216 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3491091203 |
|
|
Mar 03 01:08:46 PM PST 24 |
Mar 03 01:16:23 PM PST 24 |
678224600 ps |
| T217 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2653577859 |
|
|
Mar 03 01:08:08 PM PST 24 |
Mar 03 01:23:37 PM PST 24 |
6589214700 ps |
| T288 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1286505667 |
|
|
Mar 03 01:08:17 PM PST 24 |
Mar 03 01:08:31 PM PST 24 |
40791500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2691363355 |
|
|
Mar 03 01:08:55 PM PST 24 |
Mar 03 01:09:10 PM PST 24 |
15185100 ps |
| T229 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3517187739 |
|
|
Mar 03 01:08:23 PM PST 24 |
Mar 03 01:08:42 PM PST 24 |
170758600 ps |
| T1134 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2755296832 |
|
|
Mar 03 01:08:47 PM PST 24 |
Mar 03 01:09:00 PM PST 24 |
18467000 ps |
| T428 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1821645547 |
|
|
Mar 03 01:07:43 PM PST 24 |
Mar 03 01:08:35 PM PST 24 |
2940446100 ps |
| T230 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2169691063 |
|
|
Mar 03 01:08:01 PM PST 24 |
Mar 03 01:08:17 PM PST 24 |
167250400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.780680924 |
|
|
Mar 03 01:08:15 PM PST 24 |
Mar 03 01:08:31 PM PST 24 |
128805400 ps |
| T1136 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1883386267 |
|
|
Mar 03 01:07:52 PM PST 24 |
Mar 03 01:08:06 PM PST 24 |
14081400 ps |
| T314 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1309924393 |
|
|
Mar 03 01:08:01 PM PST 24 |
Mar 03 01:08:14 PM PST 24 |
17930100 ps |
| T289 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1662096456 |
|
|
Mar 03 01:08:49 PM PST 24 |
Mar 03 01:09:04 PM PST 24 |
56659500 ps |
| T290 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2803644323 |
|
|
Mar 03 01:07:47 PM PST 24 |
Mar 03 01:08:31 PM PST 24 |
3630789700 ps |
| T291 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3238550119 |
|
|
Mar 03 01:07:54 PM PST 24 |
Mar 03 01:08:11 PM PST 24 |
69577600 ps |
| T1137 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4152604322 |
|
|
Mar 03 01:08:38 PM PST 24 |
Mar 03 01:08:54 PM PST 24 |
23612900 ps |
| T1138 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2411631055 |
|
|
Mar 03 01:07:51 PM PST 24 |
Mar 03 01:08:29 PM PST 24 |
324964400 ps |
| T316 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1713054943 |
|
|
Mar 03 01:09:05 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
16266400 ps |
| T257 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.438237412 |
|
|
Mar 03 01:08:14 PM PST 24 |
Mar 03 01:08:34 PM PST 24 |
100392400 ps |
| T296 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2940820433 |
|
|
Mar 03 01:08:15 PM PST 24 |
Mar 03 01:08:32 PM PST 24 |
239179300 ps |
| T292 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.360847028 |
|
|
Mar 03 01:08:14 PM PST 24 |
Mar 03 01:08:50 PM PST 24 |
898044000 ps |
| T1139 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.897102662 |
|
|
Mar 03 01:08:49 PM PST 24 |
Mar 03 01:09:06 PM PST 24 |
17615800 ps |
| T1140 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2191680247 |
|
|
Mar 03 01:07:58 PM PST 24 |
Mar 03 01:08:11 PM PST 24 |
13770300 ps |
| T1141 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3363205472 |
|
|
Mar 03 01:08:53 PM PST 24 |
Mar 03 01:09:10 PM PST 24 |
31660700 ps |
| T265 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1438416029 |
|
|
Mar 03 01:08:06 PM PST 24 |
Mar 03 01:08:27 PM PST 24 |
55096300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1779486209 |
|
|
Mar 03 01:07:45 PM PST 24 |
Mar 03 01:08:52 PM PST 24 |
6333321600 ps |
| T266 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.670159223 |
|
|
Mar 03 01:08:48 PM PST 24 |
Mar 03 01:09:04 PM PST 24 |
101774100 ps |
| T293 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3854636975 |
|
|
Mar 03 01:08:38 PM PST 24 |
Mar 03 01:08:56 PM PST 24 |
98942100 ps |
| T294 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1897770148 |
|
|
Mar 03 01:08:41 PM PST 24 |
Mar 03 01:08:59 PM PST 24 |
245967100 ps |
| T258 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.874990592 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:08:04 PM PST 24 |
59675700 ps |
| T267 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2729726787 |
|
|
Mar 03 01:08:00 PM PST 24 |
Mar 03 01:08:20 PM PST 24 |
753909500 ps |
| T315 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2407968105 |
|
|
Mar 03 01:08:46 PM PST 24 |
Mar 03 01:08:59 PM PST 24 |
16580000 ps |
| T1143 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.772052222 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:16 PM PST 24 |
15323100 ps |
| T1144 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3621810131 |
|
|
Mar 03 01:07:51 PM PST 24 |
Mar 03 01:08:08 PM PST 24 |
197726400 ps |
| T1145 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1483186105 |
|
|
Mar 03 01:07:50 PM PST 24 |
Mar 03 01:08:03 PM PST 24 |
24260000 ps |
| T1146 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3345248121 |
|
|
Mar 03 01:08:01 PM PST 24 |
Mar 03 01:08:47 PM PST 24 |
79002400 ps |
| T262 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1049237957 |
|
|
Mar 03 01:08:45 PM PST 24 |
Mar 03 01:09:05 PM PST 24 |
103830300 ps |
| T333 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.136537555 |
|
|
Mar 03 01:08:24 PM PST 24 |
Mar 03 01:23:09 PM PST 24 |
694741600 ps |
| T1147 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3892132232 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:07:59 PM PST 24 |
89188700 ps |
| T233 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1326787205 |
|
|
Mar 03 01:07:46 PM PST 24 |
Mar 03 01:08:00 PM PST 24 |
47401600 ps |
| T1148 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3297610224 |
|
|
Mar 03 01:07:59 PM PST 24 |
Mar 03 01:08:16 PM PST 24 |
34054800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.4102892548 |
|
|
Mar 03 01:09:11 PM PST 24 |
Mar 03 01:09:25 PM PST 24 |
27829200 ps |
| T1150 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4052074835 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:07:58 PM PST 24 |
31090200 ps |
| T234 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3009354069 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:07 PM PST 24 |
24704000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2855489496 |
|
|
Mar 03 01:08:50 PM PST 24 |
Mar 03 01:09:04 PM PST 24 |
12688600 ps |
| T1152 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3825647876 |
|
|
Mar 03 01:08:15 PM PST 24 |
Mar 03 01:08:31 PM PST 24 |
41919500 ps |
| T1153 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1482022735 |
|
|
Mar 03 01:08:04 PM PST 24 |
Mar 03 01:08:23 PM PST 24 |
101274300 ps |
| T295 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2373837149 |
|
|
Mar 03 01:08:55 PM PST 24 |
Mar 03 01:23:49 PM PST 24 |
880058400 ps |
| T297 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.17873247 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:08:27 PM PST 24 |
439996400 ps |
| T1154 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3553746435 |
|
|
Mar 03 01:08:48 PM PST 24 |
Mar 03 01:09:04 PM PST 24 |
66276400 ps |
| T301 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3036595217 |
|
|
Mar 03 01:08:17 PM PST 24 |
Mar 03 01:08:35 PM PST 24 |
180259000 ps |
| T1155 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.910971546 |
|
|
Mar 03 01:08:16 PM PST 24 |
Mar 03 01:08:30 PM PST 24 |
29122700 ps |
| T1156 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4093702660 |
|
|
Mar 03 01:08:55 PM PST 24 |
Mar 03 01:09:13 PM PST 24 |
168623600 ps |
| T1157 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3924437240 |
|
|
Mar 03 01:08:56 PM PST 24 |
Mar 03 01:09:14 PM PST 24 |
128538600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1510600120 |
|
|
Mar 03 01:08:39 PM PST 24 |
Mar 03 01:08:53 PM PST 24 |
34826800 ps |
| T1159 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2773610927 |
|
|
Mar 03 01:08:49 PM PST 24 |
Mar 03 01:09:05 PM PST 24 |
12133000 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1971914129 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:08:49 PM PST 24 |
1759227300 ps |
| T1161 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1217435895 |
|
|
Mar 03 01:09:04 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
17034600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1895281520 |
|
|
Mar 03 01:08:13 PM PST 24 |
Mar 03 01:08:31 PM PST 24 |
26741900 ps |
| T1163 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.306302555 |
|
|
Mar 03 01:08:09 PM PST 24 |
Mar 03 01:08:24 PM PST 24 |
123544100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3051780964 |
|
|
Mar 03 01:08:46 PM PST 24 |
Mar 03 01:09:00 PM PST 24 |
141955500 ps |
| T298 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1944381369 |
|
|
Mar 03 01:08:00 PM PST 24 |
Mar 03 01:08:16 PM PST 24 |
98495000 ps |
| T1165 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.4251386954 |
|
|
Mar 03 01:09:12 PM PST 24 |
Mar 03 01:09:26 PM PST 24 |
17417400 ps |
| T1166 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2987631768 |
|
|
Mar 03 01:07:45 PM PST 24 |
Mar 03 01:08:01 PM PST 24 |
84825900 ps |
| T339 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2000529153 |
|
|
Mar 03 01:08:16 PM PST 24 |
Mar 03 01:20:56 PM PST 24 |
1605273100 ps |
| T1167 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3090075805 |
|
|
Mar 03 01:08:54 PM PST 24 |
Mar 03 01:09:10 PM PST 24 |
35007400 ps |
| T1168 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.74023595 |
|
|
Mar 03 01:09:14 PM PST 24 |
Mar 03 01:09:28 PM PST 24 |
18116000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.253836112 |
|
|
Mar 03 01:09:11 PM PST 24 |
Mar 03 01:09:25 PM PST 24 |
32574700 ps |
| T1170 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2759271917 |
|
|
Mar 03 01:08:17 PM PST 24 |
Mar 03 01:08:35 PM PST 24 |
48036300 ps |
| T1171 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3151072830 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:08:27 PM PST 24 |
95040700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.172997934 |
|
|
Mar 03 01:07:50 PM PST 24 |
Mar 03 01:08:21 PM PST 24 |
30757300 ps |
| T1173 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1681082327 |
|
|
Mar 03 01:08:53 PM PST 24 |
Mar 03 01:09:08 PM PST 24 |
64517200 ps |
| T300 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4223763707 |
|
|
Mar 03 01:07:51 PM PST 24 |
Mar 03 01:08:09 PM PST 24 |
401705300 ps |
| T1174 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3619988788 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:16 PM PST 24 |
58908200 ps |
| T1175 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3644868641 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:08:23 PM PST 24 |
66255600 ps |
| T299 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2597338443 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:20:46 PM PST 24 |
3234316100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.469625511 |
|
|
Mar 03 01:08:23 PM PST 24 |
Mar 03 01:08:43 PM PST 24 |
270338700 ps |
| T1177 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4176097986 |
|
|
Mar 03 01:08:14 PM PST 24 |
Mar 03 01:08:29 PM PST 24 |
160171200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3203899469 |
|
|
Mar 03 01:07:59 PM PST 24 |
Mar 03 01:08:49 PM PST 24 |
5356446100 ps |
| T1179 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.378377253 |
|
|
Mar 03 01:09:04 PM PST 24 |
Mar 03 01:09:18 PM PST 24 |
42979400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.145161450 |
|
|
Mar 03 01:08:06 PM PST 24 |
Mar 03 01:08:25 PM PST 24 |
443604200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2811816833 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:08 PM PST 24 |
218821800 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2703197209 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:15:29 PM PST 24 |
347073000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3415653979 |
|
|
Mar 03 01:09:06 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
16527600 ps |
| T1183 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.4216082668 |
|
|
Mar 03 01:07:46 PM PST 24 |
Mar 03 01:08:02 PM PST 24 |
11606900 ps |
| T334 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3450297917 |
|
|
Mar 03 01:08:47 PM PST 24 |
Mar 03 01:16:25 PM PST 24 |
347570700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.412623412 |
|
|
Mar 03 01:08:09 PM PST 24 |
Mar 03 01:08:22 PM PST 24 |
16366800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3129134074 |
|
|
Mar 03 01:08:54 PM PST 24 |
Mar 03 01:09:08 PM PST 24 |
18128400 ps |
| T1186 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1090636996 |
|
|
Mar 03 01:09:05 PM PST 24 |
Mar 03 01:09:19 PM PST 24 |
20948300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3434266127 |
|
|
Mar 03 01:07:52 PM PST 24 |
Mar 03 01:09:18 PM PST 24 |
3216854000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2075921099 |
|
|
Mar 03 01:08:54 PM PST 24 |
Mar 03 01:09:12 PM PST 24 |
31192100 ps |
| T1189 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4132074631 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:08:06 PM PST 24 |
175375900 ps |
| T1190 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2919094607 |
|
|
Mar 03 01:09:02 PM PST 24 |
Mar 03 01:09:37 PM PST 24 |
67938000 ps |
| T1191 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2781816397 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:06 PM PST 24 |
40617100 ps |
| T1192 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3894226710 |
|
|
Mar 03 01:08:48 PM PST 24 |
Mar 03 01:09:24 PM PST 24 |
323308700 ps |
| T1193 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1625366826 |
|
|
Mar 03 01:08:16 PM PST 24 |
Mar 03 01:08:32 PM PST 24 |
74657800 ps |
| T235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3195714275 |
|
|
Mar 03 01:08:01 PM PST 24 |
Mar 03 01:08:14 PM PST 24 |
14825500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3739504978 |
|
|
Mar 03 01:09:05 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
29457400 ps |
| T1195 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.901980262 |
|
|
Mar 03 01:07:51 PM PST 24 |
Mar 03 01:08:11 PM PST 24 |
46827600 ps |
| T1196 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1419971899 |
|
|
Mar 03 01:09:06 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
15095100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2646359901 |
|
|
Mar 03 01:09:05 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
31999500 ps |
| T302 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3599307674 |
|
|
Mar 03 01:08:47 PM PST 24 |
Mar 03 01:09:17 PM PST 24 |
383188000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1566616094 |
|
|
Mar 03 01:09:06 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
182024700 ps |
| T1199 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3851757023 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:08:24 PM PST 24 |
140146300 ps |
| T1200 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.593596959 |
|
|
Mar 03 01:09:04 PM PST 24 |
Mar 03 01:09:18 PM PST 24 |
47688500 ps |
| T1201 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3767274889 |
|
|
Mar 03 01:07:43 PM PST 24 |
Mar 03 01:07:59 PM PST 24 |
18009300 ps |
| T1202 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3687369608 |
|
|
Mar 03 01:07:58 PM PST 24 |
Mar 03 01:08:11 PM PST 24 |
19068900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2349243828 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:08:27 PM PST 24 |
593595400 ps |
| T1204 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3887226569 |
|
|
Mar 03 01:08:24 PM PST 24 |
Mar 03 01:08:57 PM PST 24 |
601322000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1596829112 |
|
|
Mar 03 01:07:45 PM PST 24 |
Mar 03 01:08:16 PM PST 24 |
32949300 ps |
| T236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.926364057 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:07 PM PST 24 |
25574200 ps |
| T1206 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.459579596 |
|
|
Mar 03 01:08:46 PM PST 24 |
Mar 03 01:09:02 PM PST 24 |
115169000 ps |
| T1207 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3054596271 |
|
|
Mar 03 01:08:45 PM PST 24 |
Mar 03 01:09:02 PM PST 24 |
55513400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.721205051 |
|
|
Mar 03 01:08:07 PM PST 24 |
Mar 03 01:08:23 PM PST 24 |
27127700 ps |
| T1209 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3283996362 |
|
|
Mar 03 01:08:40 PM PST 24 |
Mar 03 01:08:56 PM PST 24 |
19724900 ps |
| T342 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2339878608 |
|
|
Mar 03 01:07:44 PM PST 24 |
Mar 03 01:14:09 PM PST 24 |
890198200 ps |
| T1210 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3170915496 |
|
|
Mar 03 01:08:00 PM PST 24 |
Mar 03 01:08:17 PM PST 24 |
48223100 ps |
| T340 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1318442014 |
|
|
Mar 03 01:08:16 PM PST 24 |
Mar 03 01:14:40 PM PST 24 |
822950500 ps |
| T1211 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3360903253 |
|
|
Mar 03 01:07:47 PM PST 24 |
Mar 03 01:08:01 PM PST 24 |
15341400 ps |
| T1212 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4248453793 |
|
|
Mar 03 01:08:48 PM PST 24 |
Mar 03 01:09:09 PM PST 24 |
624138400 ps |
| T1213 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3413277357 |
|
|
Mar 03 01:08:22 PM PST 24 |
Mar 03 01:08:38 PM PST 24 |
16514700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.92157607 |
|
|
Mar 03 01:09:05 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
16677100 ps |
| T1215 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3203752107 |
|
|
Mar 03 01:08:14 PM PST 24 |
Mar 03 01:08:28 PM PST 24 |
18319300 ps |
| T1216 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2317573230 |
|
|
Mar 03 01:08:47 PM PST 24 |
Mar 03 01:09:00 PM PST 24 |
15931300 ps |
| T336 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3382710862 |
|
|
Mar 03 01:07:47 PM PST 24 |
Mar 03 01:22:38 PM PST 24 |
3138932000 ps |
| T1217 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3580103516 |
|
|
Mar 03 01:09:11 PM PST 24 |
Mar 03 01:09:25 PM PST 24 |
25666700 ps |
| T337 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3779649434 |
|
|
Mar 03 01:08:40 PM PST 24 |
Mar 03 01:23:57 PM PST 24 |
360280400 ps |
| T1218 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.297512493 |
|
|
Mar 03 01:07:43 PM PST 24 |
Mar 03 01:07:57 PM PST 24 |
26019700 ps |
| T341 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2301098276 |
|
|
Mar 03 01:08:51 PM PST 24 |
Mar 03 01:16:36 PM PST 24 |
2091656200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3734921603 |
|
|
Mar 03 01:08:46 PM PST 24 |
Mar 03 01:09:02 PM PST 24 |
165307500 ps |
| T1220 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2414642432 |
|
|
Mar 03 01:09:12 PM PST 24 |
Mar 03 01:09:25 PM PST 24 |
15157000 ps |
| T1221 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.692789151 |
|
|
Mar 03 01:08:39 PM PST 24 |
Mar 03 01:08:53 PM PST 24 |
21739300 ps |
| T264 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.113521827 |
|
|
Mar 03 01:08:39 PM PST 24 |
Mar 03 01:23:30 PM PST 24 |
3022123100 ps |
| T1222 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4231427375 |
|
|
Mar 03 01:08:15 PM PST 24 |
Mar 03 01:08:28 PM PST 24 |
166865200 ps |
| T1223 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.350716471 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:17 PM PST 24 |
61639800 ps |
| T1224 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.530831659 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:17 PM PST 24 |
56881300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2239435821 |
|
|
Mar 03 01:09:06 PM PST 24 |
Mar 03 01:09:20 PM PST 24 |
30959900 ps |
| T1226 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1870259364 |
|
|
Mar 03 01:08:53 PM PST 24 |
Mar 03 01:09:07 PM PST 24 |
61170600 ps |
| T1227 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3667575701 |
|
|
Mar 03 01:08:05 PM PST 24 |
Mar 03 01:08:21 PM PST 24 |
38040700 ps |
| T1228 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1965568498 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:17 PM PST 24 |
24016400 ps |
| T335 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1885329217 |
|
|
Mar 03 01:08:54 PM PST 24 |
Mar 03 01:23:48 PM PST 24 |
5507034900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.145079683 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:07 PM PST 24 |
16654800 ps |
| T1230 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1864316689 |
|
|
Mar 03 01:08:01 PM PST 24 |
Mar 03 01:08:15 PM PST 24 |
17179400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2166849288 |
|
|
Mar 03 01:07:51 PM PST 24 |
Mar 03 01:08:04 PM PST 24 |
23594300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.330321628 |
|
|
Mar 03 01:08:24 PM PST 24 |
Mar 03 01:08:37 PM PST 24 |
14502700 ps |
| T1233 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2292640604 |
|
|
Mar 03 01:08:11 PM PST 24 |
Mar 03 01:08:30 PM PST 24 |
445277900 ps |
| T1234 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2761928058 |
|
|
Mar 03 01:08:16 PM PST 24 |
Mar 03 01:08:32 PM PST 24 |
15247400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.384285845 |
|
|
Mar 03 01:09:03 PM PST 24 |
Mar 03 01:09:17 PM PST 24 |
31808800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1986018494 |
|
|
Mar 03 01:08:46 PM PST 24 |
Mar 03 01:08:59 PM PST 24 |
49215600 ps |
| T1237 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.4150929236 |
|
|
Mar 03 01:09:04 PM PST 24 |
Mar 03 01:09:21 PM PST 24 |
50238600 ps |
| T1238 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3342443167 |
|
|
Mar 03 01:08:56 PM PST 24 |
Mar 03 01:09:15 PM PST 24 |
73712900 ps |
| T1239 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2823604608 |
|
|
Mar 03 01:08:46 PM PST 24 |
Mar 03 01:09:02 PM PST 24 |
117643400 ps |
| T1240 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2492188952 |
|
|
Mar 03 01:08:54 PM PST 24 |
Mar 03 01:09:13 PM PST 24 |
467428400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1038243415 |
|
|
Mar 03 01:09:10 PM PST 24 |
Mar 03 01:09:24 PM PST 24 |
27780200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.490372374 |
|
|
Mar 03 01:08:09 PM PST 24 |
Mar 03 01:08:23 PM PST 24 |
17688700 ps |
| T1243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3910509687 |
|
|
Mar 03 01:07:50 PM PST 24 |
Mar 03 01:08:04 PM PST 24 |
18385100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4211128687 |
|
|
Mar 03 01:08:23 PM PST 24 |
Mar 03 01:08:37 PM PST 24 |
58146200 ps |
| T1245 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4001033726 |
|
|
Mar 03 01:07:53 PM PST 24 |
Mar 03 01:08:26 PM PST 24 |
237311000 ps |
| T1246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2678559659 |
|
|
Mar 03 01:07:52 PM PST 24 |
Mar 03 01:08:27 PM PST 24 |
872317200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1170269341 |
|
|
Mar 03 01:08:38 PM PST 24 |
Mar 03 01:08:55 PM PST 24 |
75119300 ps |
| T1248 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1971729917 |
|
|
Mar 03 01:07:46 PM PST 24 |
Mar 03 01:08:02 PM PST 24 |
18890800 ps |
| T1249 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3019323141 |
|
|
Mar 03 01:08:48 PM PST 24 |
Mar 03 01:09:05 PM PST 24 |
49263400 ps |
| T1250 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.165024486 |
|
|
Mar 03 01:08:14 PM PST 24 |
Mar 03 01:08:31 PM PST 24 |
122764000 ps |
| T1251 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3041176928 |
|
|
Mar 03 01:08:50 PM PST 24 |
Mar 03 01:09:07 PM PST 24 |
43836800 ps |