Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22515901	1		T1	140		T2	86		T3	113
full_word	6584615	1		T1	64		T2	50		T3	109

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29100216	1		T1	204		T2	136		T3	222
auto[TlIntgErrCmd]	110	1		T244	10		T265	4		T266	4
auto[TlIntgErrData]	96	1		T244	7		T265	8		T266	2
auto[TlIntgErrBoth]	94	1		T244	3		T265	8		T266	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25388959	1		T1	148		T2	58		T3	158
auto[1]	3711557	1		T1	56		T2	78		T3	64

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21934258	1		T1	134		T2	58		T3	98
auto[TlIntgErrNone]	partial	auto[1]	581372	1		T1	6		T2	28		T3	15
auto[TlIntgErrNone]	full_word	auto[0]	3454570	1		T1	14		T3	60		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3130016	1		T1	50		T2	50		T3	49
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T244	4		T266	1		T368	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T244	5		T265	3		T266	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T244	1		T265	1		T287	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T266	1		T375	1		T368	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T244	4		T265	5		T266	1
auto[TlIntgErrData]	partial	auto[1]	39	1		T244	3		T265	2		T368	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T265	1		T266	1		T376	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T294	1		T376	1		T369	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T244	2		T265	3		T266	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T244	1		T265	4		T266	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T265	1		T266	1		T377	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T368	1		T376	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17985	1		T37	556		T203	993		T201	51
full_word	3907298	1		T5	16801		T16	10		T8	16676

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3925006	1		T5	16801		T16	10		T8	16676
auto[TlIntgErrCmd]	86	1		T244	6		T265	7		T266	3
auto[TlIntgErrData]	105	1		T244	8		T265	7		T266	5
auto[TlIntgErrBoth]	86	1		T244	4		T265	4		T266	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3901861	1		T5	16801		T16	10		T8	16676
auto[1]	23422	1		T37	587		T203	1320		T201	55

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1074	1		T37	43		T203	28		T201	1
auto[TlIntgErrNone]	partial	auto[1]	16661	1		T37	513		T203	965		T201	50
auto[TlIntgErrNone]	full_word	auto[0]	3900673	1		T5	16801		T16	10		T8	16676
auto[TlIntgErrNone]	full_word	auto[1]	6598	1		T37	74		T203	355		T201	5
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T244	3		T265	2		T368	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T244	2		T265	5		T266	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T376	3		T369	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T244	1		T287	1		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1		T244	3		T265	2		T266	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T244	4		T265	3		T266	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T244	1		T368	1		T287	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T265	2		T266	1		T368	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T244	1		T265	2		T266	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T244	2		T265	2		T266	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T244	1		T368	1		T370	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T294	1		T291	1		T378	1