Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_chk.u_chk	100.00			100.00
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	100.00			100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk	100.00			100.00

---

Module Instance : tb.dut.u_reg_core.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T3,T4	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
err_o[1:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_core.u_chk.u_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T3,T4	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T4,T6,T8	Yes	T4,T6,T8	OUTPUT
err_o[1:0]	Yes	Yes	T4,T6,T8	Yes	T4,T6,T8	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T5,*T16,*T8	Yes	T1,T5,T16	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T5,T16,T8	Yes	T5,T16,T8	INPUT
data_o[56:0]	Yes	Yes	T5,T16,T8	Yes	T1,T5,T16	OUTPUT
syndrome_o[6:0]	Yes	Yes	T19,T20,T144	Yes	T19,T20,T28	OUTPUT
err_o[1:0]	Yes	Yes	T5,T16,T8	Yes	T5,T16,T8	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T5,*T7,*T19	Yes	T58,T33,T153	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T7,T19,T33	Yes	T5,T7,T19	INPUT
data_o[56:0]	Yes	Yes	T5,T7,T19	Yes	T58,T33,T153	OUTPUT
syndrome_o[6:0]	Yes	Yes	T5,T70,T200	Yes	T5,T58,T33	OUTPUT
err_o[1:0]	Yes	Yes	T19,T153,T51	Yes	T5,T22,T153	OUTPUT

*Tests covering at least one bit in the range