Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T16,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T16,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T16,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T16,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T16,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T16,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T16,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1564139780	1560908908	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1564139780	433255342	0	0
GntImpliesValid_A	1564139780	433255342	0	0
GrantKnown_A	1564139780	1560908908	0	0
IdxKnown_A	1564139780	1560908908	0	0
IndexIsCorrect_A	1564139780	433255342	0	0
NoReadyValidNoGrant_A	1564139780	178830383	0	0
Priority_A	1564139780	456760299	0	0
ReadyAndValidImplyGrant_A	1564139780	433255342	0	0
ReqAndReadyImplyGrant_A	1564139780	433255342	0	0
ReqImpliesValid_A	1564139780	456760299	0	0
ValidKnown_A	1564139780	1560908908	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	1560908908	0	0
T1	4656	4380	0	0
T2	7508	7256	0	0
T3	1536132	1536072	0	0
T4	320768	320508	0	0
T5	495812	495156	0	0
T6	387200	386824	0	0
T7	486552	486056	0	0
T8	461996	461412	0	0
T16	18996	17988	0	0
T17	3412	3212	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	433255342	0	0
T1	2328	326	0	0
T2	3754	64	0	0
T3	1536132	514652	0	0
T4	320768	33774	0	0
T5	495812	68226	0	0
T6	387200	121852	0	0
T7	486552	67332	0	0
T8	461996	75082	0	0
T16	18996	1974	0	0
T17	3412	64	0	0
T19	0	29268	0	0
T56	234076	31772	0	0
T57	0	20610	0	0
T59	2994	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	433255342	0	0
T1	2328	326	0	0
T2	3754	64	0	0
T3	1536132	514652	0	0
T4	320768	33774	0	0
T5	495812	68226	0	0
T6	387200	121852	0	0
T7	486552	67332	0	0
T8	461996	75082	0	0
T16	18996	1974	0	0
T17	3412	64	0	0
T19	0	29268	0	0
T56	234076	31772	0	0
T57	0	20610	0	0
T59	2994	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	1560908908	0	0
T1	4656	4380	0	0
T2	7508	7256	0	0
T3	1536132	1536072	0	0
T4	320768	320508	0	0
T5	495812	495156	0	0
T6	387200	386824	0	0
T7	486552	486056	0	0
T8	461996	461412	0	0
T16	18996	17988	0	0
T17	3412	3212	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	1560908908	0	0
T1	4656	4380	0	0
T2	7508	7256	0	0
T3	1536132	1536072	0	0
T4	320768	320508	0	0
T5	495812	495156	0	0
T6	387200	386824	0	0
T7	486552	486056	0	0
T8	461996	461412	0	0
T16	18996	17988	0	0
T17	3412	3212	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	433255342	0	0
T1	2328	326	0	0
T2	3754	64	0	0
T3	1536132	514652	0	0
T4	320768	33774	0	0
T5	495812	68226	0	0
T6	387200	121852	0	0
T7	486552	67332	0	0
T8	461996	75082	0	0
T16	18996	1974	0	0
T17	3412	64	0	0
T19	0	29268	0	0
T56	234076	31772	0	0
T57	0	20610	0	0
T59	2994	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	178830383	0	0
T1	2328	322	0	0
T2	3754	256	0	0
T3	1536132	2109952	0	0
T4	320768	256	0	0
T5	495812	181752	0	0
T6	387200	7372	0	0
T7	486552	182026	0	0
T8	461996	120822	0	0
T16	18996	842	0	0
T17	3412	256	0	0
T19	0	77338	0	0
T39	0	84	0	0
T56	234076	85232	0	0
T58	0	126	0	0
T59	2994	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	456760299	0	0
T1	2328	326	0	0
T2	3754	64	0	0
T3	1536132	514652	0	0
T4	320768	33774	0	0
T5	495812	72024	0	0
T6	387200	121852	0	0
T7	486552	70142	0	0
T8	461996	85478	0	0
T16	18996	1974	0	0
T17	3412	64	0	0
T19	0	30276	0	0
T56	234076	33466	0	0
T57	0	20610	0	0
T59	2994	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	433255342	0	0
T1	2328	326	0	0
T2	3754	64	0	0
T3	1536132	514652	0	0
T4	320768	33774	0	0
T5	495812	68226	0	0
T6	387200	121852	0	0
T7	486552	67332	0	0
T8	461996	75082	0	0
T16	18996	1974	0	0
T17	3412	64	0	0
T19	0	29268	0	0
T56	234076	31772	0	0
T57	0	20610	0	0
T59	2994	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	433255342	0	0
T1	2328	326	0	0
T2	3754	64	0	0
T3	1536132	514652	0	0
T4	320768	33774	0	0
T5	495812	68226	0	0
T6	387200	121852	0	0
T7	486552	67332	0	0
T8	461996	75082	0	0
T16	18996	1974	0	0
T17	3412	64	0	0
T19	0	29268	0	0
T56	234076	31772	0	0
T57	0	20610	0	0
T59	2994	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	456760299	0	0
T1	2328	326	0	0
T2	3754	64	0	0
T3	1536132	514652	0	0
T4	320768	33774	0	0
T5	495812	72024	0	0
T6	387200	121852	0	0
T7	486552	70142	0	0
T8	461996	85478	0	0
T16	18996	1974	0	0
T17	3412	64	0	0
T19	0	30276	0	0
T56	234076	33466	0	0
T57	0	20610	0	0
T59	2994	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1564139780	1560908908	0	0
T1	4656	4380	0	0
T2	7508	7256	0	0
T3	1536132	1536072	0	0
T4	320768	320508	0	0
T5	495812	495156	0	0
T6	387200	386824	0	0
T7	486552	486056	0	0
T8	461996	461412	0	0
T16	18996	17988	0	0
T17	3412	3212	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T16,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T16,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T16,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T16,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T16,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T16,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T16,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391034945	390227227	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391034945	116031720	0	0
GntImpliesValid_A	391034945	116031720	0	0
GrantKnown_A	391034945	390227227	0	0
IdxKnown_A	391034945	390227227	0	0
IndexIsCorrect_A	391034945	116031720	0	0
NoReadyValidNoGrant_A	391034945	46282638	0	0
Priority_A	391034945	122089596	0	0
ReadyAndValidImplyGrant_A	391034945	116031720	0	0
ReqAndReadyImplyGrant_A	391034945	116031720	0	0
ReqImpliesValid_A	391034945	122089596	0	0
ValidKnown_A	391034945	390227227	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	116031720	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	116031720	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	116031720	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	46282638	0	0
T1	1164	161	0	0
T2	1877	128	0	0
T3	384033	530688	0	0
T4	80192	128	0	0
T5	123953	52674	0	0
T6	96800	1688	0	0
T7	121638	46268	0	0
T8	115499	38983	0	0
T16	4749	416	0	0
T17	853	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	122089596	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	21144	0	0
T6	96800	26772	0	0
T7	121638	17994	0	0
T8	115499	25337	0	0
T16	4749	377	0	0
T17	853	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	116031720	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	116031720	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	122089596	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	21144	0	0
T6	96800	26772	0	0
T7	121638	17994	0	0
T8	115499	25337	0	0
T16	4749	377	0	0
T17	853	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T16,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T16,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T16,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T16,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T16,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T16,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T16,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391034945	390227227	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391034945	115892570	0	0
GntImpliesValid_A	391034945	115892570	0	0
GrantKnown_A	391034945	390227227	0	0
IdxKnown_A	391034945	390227227	0	0
IndexIsCorrect_A	391034945	115892570	0	0
NoReadyValidNoGrant_A	391034945	46282641	0	0
Priority_A	391034945	121950443	0	0
ReadyAndValidImplyGrant_A	391034945	115892570	0	0
ReqAndReadyImplyGrant_A	391034945	115892570	0	0
ReqImpliesValid_A	391034945	121950443	0	0
ValidKnown_A	391034945	390227227	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	115892570	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	115892570	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	115892570	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	46282641	0	0
T1	1164	161	0	0
T2	1877	128	0	0
T3	384033	530688	0	0
T4	80192	128	0	0
T5	123953	52674	0	0
T6	96800	1688	0	0
T7	121638	46268	0	0
T8	115499	38983	0	0
T16	4749	416	0	0
T17	853	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	121950443	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	21144	0	0
T6	96800	26772	0	0
T7	121638	17994	0	0
T8	115499	25337	0	0
T16	4749	377	0	0
T17	853	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	115892570	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	115892570	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	19948	0	0
T6	96800	26772	0	0
T7	121638	17221	0	0
T8	115499	22554	0	0
T16	4749	377	0	0
T17	853	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	121950443	0	0
T1	1164	163	0	0
T2	1877	32	0	0
T3	384033	129429	0	0
T4	80192	8319	0	0
T5	123953	21144	0	0
T6	96800	26772	0	0
T7	121638	17994	0	0
T8	115499	25337	0	0
T16	4749	377	0	0
T17	853	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T8,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T8,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T8,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T8,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T7
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T7
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391034945	390227227	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391034945	100665526	0	0
GntImpliesValid_A	391034945	100665526	0	0
GrantKnown_A	391034945	390227227	0	0
IdxKnown_A	391034945	390227227	0	0
IndexIsCorrect_A	391034945	100665526	0	0
NoReadyValidNoGrant_A	391034945	43132552	0	0
Priority_A	391034945	106360130	0	0
ReadyAndValidImplyGrant_A	391034945	100665526	0	0
ReqAndReadyImplyGrant_A	391034945	100665526	0	0
ReqImpliesValid_A	391034945	106360130	0	0
ValidKnown_A	391034945	390227227	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	43132552	0	0
T3	384033	524288	0	0
T4	80192	0	0	0
T5	123953	38202	0	0
T6	96800	1998	0	0
T7	121638	44745	0	0
T8	115499	21428	0	0
T16	4749	5	0	0
T17	853	0	0	0
T19	0	38669	0	0
T39	0	42	0	0
T56	117038	42616	0	0
T58	0	63	0	0
T59	1497	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	106360130	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14868	0	0
T6	96800	34154	0	0
T7	121638	17077	0	0
T8	115499	17402	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	15138	0	0
T56	117038	16733	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	106360130	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14868	0	0
T6	96800	34154	0	0
T7	121638	17077	0	0
T8	115499	17402	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	15138	0	0
T56	117038	16733	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T8,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T8,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T8,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T8,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T7
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T7
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391034945	390227227	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391034945	100665526	0	0
GntImpliesValid_A	391034945	100665526	0	0
GrantKnown_A	391034945	390227227	0	0
IdxKnown_A	391034945	390227227	0	0
IndexIsCorrect_A	391034945	100665526	0	0
NoReadyValidNoGrant_A	391034945	43132552	0	0
Priority_A	391034945	106360130	0	0
ReadyAndValidImplyGrant_A	391034945	100665526	0	0
ReqAndReadyImplyGrant_A	391034945	100665526	0	0
ReqImpliesValid_A	391034945	106360130	0	0
ValidKnown_A	391034945	390227227	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	43132552	0	0
T3	384033	524288	0	0
T4	80192	0	0	0
T5	123953	38202	0	0
T6	96800	1998	0	0
T7	121638	44745	0	0
T8	115499	21428	0	0
T16	4749	5	0	0
T17	853	0	0	0
T19	0	38669	0	0
T39	0	42	0	0
T56	117038	42616	0	0
T58	0	63	0	0
T59	1497	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	106360130	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14868	0	0
T6	96800	34154	0	0
T7	121638	17077	0	0
T8	115499	17402	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	15138	0	0
T56	117038	16733	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	100665526	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14165	0	0
T6	96800	34154	0	0
T7	121638	16445	0	0
T8	115499	14987	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	14634	0	0
T56	117038	15886	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	106360130	0	0
T3	384033	127897	0	0
T4	80192	8568	0	0
T5	123953	14868	0	0
T6	96800	34154	0	0
T7	121638	17077	0	0
T8	115499	17402	0	0
T16	4749	610	0	0
T17	853	0	0	0
T19	0	15138	0	0
T56	117038	16733	0	0
T57	0	10305	0	0
T59	1497	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0