Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.37	100.00	96.83		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.37	100.00	96.83		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.37	100.00	96.83		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.37	100.00	96.83		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.47	100.00	96.83	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.28		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.37	100.00	96.83		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.64	100.00	96.83	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		93	93	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	50	50	100.00
ALWAYS	299	10	10	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244		unreachable
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305		unreachable
306		unreachable
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	63	61	96.83
Logical	63	61	96.83
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T134,T170,T171
1	0	Covered	T134,T170,T171

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T134,T170,T171

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T134,T170,T171
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T16,T57

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T16

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T9,T14
1	Covered	T1,T4,T16

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T16,T57

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T9,T14
1	Covered	T4,T16,T57

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T16,T6
1	Covered	T1,T3,T32

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T16,T6
1	Covered	T1,T3,T4

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T16,T6
1	Covered	T1,T3,T4

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T6
1	1	Covered	T1,T3,T4

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Covered	T1,T3,T32
1	1	Unreachable	T1,T3,T32

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T32
1	1	Covered	T1,T3,T32

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T3,T32
StCalcMask	237	Covered	T1,T3,T32
StCalcPlainEcc	215	Covered	T1,T3,T4
StDisabled	193	Covered	T3,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T3,T4
StPostPack	218	Covered	T4,T16,T57
StPrePack	195	Covered	T1,T4,T16
StReqFlash	237	Covered	T1,T3,T4
StScrambleData	244	Covered	T1,T3,T32
StWaitFlash	270	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T3,T32
StCalcMask->StScrambleData	244	Covered	T1,T3,T32
StCalcPlainEcc->StCalcMask	237	Covered	T1,T3,T32
StCalcPlainEcc->StReqFlash	237	Covered	T4,T16,T6
StIdle->StDisabled	193	Covered	T3,T12,T13
StIdle->StPackData	197	Covered	T1,T3,T4
StIdle->StPrePack	195	Covered	T1,T4,T16
StPackData->StCalcPlainEcc	215	Covered	T1,T3,T4
StPackData->StPostPack	218	Covered	T4,T16,T57
StPostPack->StCalcPlainEcc	231	Covered	T4,T16,T57
StPrePack->StPackData	205	Covered	T1,T4,T16
StReqFlash->StIdle	273	Covered	T1,T3,T4
StReqFlash->StWaitFlash	270	Covered	T1,T3,T4
StScrambleData->StCalcEcc	252	Covered	T1,T3,T32
StWaitFlash->StIdle	280	Covered	T1,T3,T4

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		53	53	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	26	26	100.00
IF	299	5	5	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T16
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T16
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T16,T57
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T16,T57
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T9,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T3,T32
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T16,T6
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable	T1,T3,T32
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T32
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T3,T32
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T3,T32
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T32
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T16,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T16,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T9,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T3,T4
0	0	1	-	-	Unreachable	T1,T3,T32
0	0	0	1	-	Covered	T1,T3,T32
0	0	0	0	1	Covered	T1,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	782069890	2368200	0	0
PostPackRule_A	782069890	30234	0	0
PrePackRule_A	782069890	15238	0	0
WidthCheck_A	2116	2116	0	0
u_state_regs_A	782069890	780454454	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782069890	2368200	0	0
T1	1164	1	0	0
T2	1877	0	0	0
T3	768066	65920	0	0
T4	160384	68	0	0
T5	247906	0	0	0
T6	193600	100	0	0
T7	243276	0	0	0
T8	230998	0	0	0
T16	9498	2	0	0
T17	1706	0	0	0
T18	0	340	0	0
T20	0	1498	0	0
T32	0	989	0	0
T39	0	61	0	0
T40	0	1	0	0
T44	0	1	0	0
T56	117038	0	0	0
T57	0	56	0	0
T59	1497	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782069890	30234	0	0
T4	160384	45	0	0
T5	247906	0	0	0
T6	193600	0	0	0
T7	243276	0	0	0
T8	230998	0	0	0
T16	9498	2	0	0
T17	1706	0	0	0
T18	0	15	0	0
T20	0	586	0	0
T21	0	1	0	0
T23	0	1	0	0
T32	0	325	0	0
T39	0	31	0	0
T56	234076	0	0	0
T57	64716	40	0	0
T59	2994	0	0	0
T72	0	12	0	0
T187	0	42	0	0
T210	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782069890	15238	0	0
T1	1164	1	0	0
T2	1877	0	0	0
T3	384033	0	0	0
T4	160384	20	0	0
T5	247906	0	0	0
T6	193600	0	0	0
T7	243276	0	0	0
T8	230998	0	0	0
T16	9498	1	0	0
T17	1706	0	0	0
T18	0	6	0	0
T20	0	292	0	0
T23	0	1	0	0
T32	0	204	0	0
T39	0	26	0	0
T44	0	1	0	0
T56	117038	0	0	0
T57	32358	29	0	0
T59	1497	0	0	0
T72	0	9	0	0
T187	0	23	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2116	2116	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782069890	780454454	0	0
T1	2328	2190	0	0
T2	3754	3628	0	0
T3	768066	768036	0	0
T4	160384	160254	0	0
T5	247906	247578	0	0
T6	193600	193412	0	0
T7	243276	243028	0	0
T8	230998	230706	0	0
T16	9498	8994	0	0
T17	1706	1606	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		93	93	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	50	50	100.00
ALWAYS	299	10	10	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244		unreachable
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305		unreachable
306		unreachable
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	63	61	96.83
Logical	63	61	96.83
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T134,T170,T171
1	0	Covered	T134,T170,T171

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T134,T170,T171

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T134,T170,T171
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T57,T39

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T57

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T9,T14
1	Covered	T1,T4,T57

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T57,T39

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T9,T14
1	Covered	T4,T57,T39

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T6,T57
1	Covered	T1,T3,T32

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T57
1	Covered	T1,T3,T4

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T57
1	Covered	T1,T3,T4

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T57
1	1	Covered	T1,T3,T4

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Covered	T1,T3,T32
1	1	Unreachable	T1,T3,T32

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T32
1	1	Covered	T1,T3,T32

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T3,T32
StCalcMask	237	Covered	T1,T3,T32
StCalcPlainEcc	215	Covered	T1,T3,T4
StDisabled	193	Covered	T3,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T3,T4
StPostPack	218	Covered	T4,T57,T39
StPrePack	195	Covered	T1,T4,T57
StReqFlash	237	Covered	T1,T3,T4
StScrambleData	244	Covered	T1,T3,T32
StWaitFlash	270	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T3,T32
StCalcMask->StScrambleData	244	Covered	T1,T3,T32
StCalcPlainEcc->StCalcMask	237	Covered	T1,T3,T32
StCalcPlainEcc->StReqFlash	237	Covered	T4,T6,T57
StIdle->StDisabled	193	Covered	T3,T12,T13
StIdle->StPackData	197	Covered	T1,T3,T4
StIdle->StPrePack	195	Covered	T1,T4,T57
StPackData->StCalcPlainEcc	215	Covered	T1,T3,T4
StPackData->StPostPack	218	Covered	T4,T57,T39
StPostPack->StCalcPlainEcc	231	Covered	T4,T57,T39
StPrePack->StPackData	205	Covered	T1,T4,T57
StReqFlash->StIdle	273	Covered	T1,T3,T4
StReqFlash->StWaitFlash	270	Covered	T1,T3,T4
StScrambleData->StCalcEcc	252	Covered	T1,T3,T32
StWaitFlash->StIdle	280	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		53	53	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	26	26	100.00
IF	299	5	5	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T57
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T57
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T57,T39
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T57,T39
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T9,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T3,T32
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T6,T57
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable	T1,T3,T32
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T32
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T3,T32
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T3,T32
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T32
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T6,T57
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T6,T57
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T9,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T3,T4
0	0	1	-	-	Unreachable	T1,T3,T32
0	0	0	1	-	Covered	T1,T3,T32
0	0	0	0	1	Covered	T1,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	391034945	1199997	0	0
PostPackRule_A	391034945	17467	0	0
PrePackRule_A	391034945	8849	0	0
WidthCheck_A	1058	1058	0	0
u_state_regs_A	391034945	390227227	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	1199997	0	0
T1	1164	1	0	0
T2	1877	0	0	0
T3	384033	33152	0	0
T4	80192	34	0	0
T5	123953	0	0	0
T6	96800	44	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	0	0	0
T17	853	0	0	0
T18	0	172	0	0
T20	0	841	0	0
T32	0	556	0	0
T39	0	29	0	0
T40	0	1	0	0
T57	0	29	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	17467	0	0
T4	80192	22	0	0
T5	123953	0	0	0
T6	96800	0	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	0	0	0
T17	853	0	0	0
T18	0	10	0	0
T20	0	254	0	0
T23	0	1	0	0
T32	0	229	0	0
T39	0	16	0	0
T56	117038	0	0	0
T57	32358	19	0	0
T59	1497	0	0	0
T72	0	6	0	0
T187	0	21	0	0
T210	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	8849	0	0
T1	1164	1	0	0
T2	1877	0	0	0
T3	384033	0	0	0
T4	80192	10	0	0
T5	123953	0	0	0
T6	96800	0	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	0	0	0
T17	853	0	0	0
T18	0	5	0	0
T20	0	167	0	0
T23	0	1	0	0
T32	0	131	0	0
T39	0	14	0	0
T57	0	11	0	0
T72	0	2	0	0
T187	0	17	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		93	93	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	50	50	100.00
ALWAYS	299	10	10	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244		unreachable
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305		unreachable
306		unreachable
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	63	61	96.83
Logical	63	61	96.83
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10
1	0	Covered	T10

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T10

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10
1	0	Covered	T3,T4,T5

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T4,T16,T57

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T16
1	0	Covered	T3,T4,T16
1	1	Covered	T3,T4,T16

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T4,T16,T57

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T9,T14
1	Covered	T4,T16,T57

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T16
1	0	Covered	T3,T4,T16
1	1	Covered	T3,T4,T16

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T3,T4,T16

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T16
1	1	Covered	T4,T16,T57

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T9,T14
1	Covered	T4,T16,T57

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T16,T6
1	Covered	T3,T32,T21

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T16,T6
1	Covered	T3,T4,T16

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T16,T6
1	Covered	T3,T4,T16

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T6
1	1	Covered	T3,T4,T16

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable	T3,T5,T8
1	0	Covered	T3,T32,T21
1	1	Unreachable	T3,T32,T21

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T3,T32,T21
1	1	Covered	T3,T32,T21

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T16
1	1	0	Covered	T3,T4,T16
1	1	1	Covered	T3,T4,T16

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T16

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T32,T21,T139
StCalcMask	237	Covered	T32,T21,T139
StCalcPlainEcc	215	Covered	T4,T16,T6
StDisabled	193	Covered	T3,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T16,T6
StPostPack	218	Covered	T4,T16,T57
StPrePack	195	Covered	T4,T16,T57
StReqFlash	237	Covered	T4,T16,T6
StScrambleData	244	Covered	T32,T21,T139
StWaitFlash	270	Covered	T3,T4,T16

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T32,T21,T139
StCalcMask->StScrambleData	244	Covered	T32,T21,T139
StCalcPlainEcc->StCalcMask	237	Covered	T32,T21,T139
StCalcPlainEcc->StReqFlash	237	Covered	T4,T16,T6
StIdle->StDisabled	193	Covered	T3,T12,T13
StIdle->StPackData	197	Covered	T4,T16,T6
StIdle->StPrePack	195	Covered	T4,T16,T57
StPackData->StCalcPlainEcc	215	Covered	T4,T16,T6
StPackData->StPostPack	218	Covered	T4,T16,T57
StPostPack->StCalcPlainEcc	231	Covered	T4,T16,T57
StPrePack->StPackData	205	Covered	T4,T16,T57
StReqFlash->StIdle	273	Covered	T3,T4,T16
StReqFlash->StWaitFlash	270	Covered	T3,T4,T16
StScrambleData->StCalcEcc	252	Covered	T32,T21,T139
StWaitFlash->StIdle	280	Covered	T3,T4,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		53	53	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	26	26	100.00
IF	299	5	5	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T16
0	1	Covered	T3,T5,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T16
0	0	1	Covered	T3,T4,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T16,T57
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T16
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T16,T57
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T16
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T16,T57
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T16
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T3,T4,T16
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T16,T57
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T9,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T32,T21
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T16,T6
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable	T3,T32,T21
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T32,T21
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T32,T21
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T32,T21
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T32,T21
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T3,T4,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T16,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T3,T4,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T16,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T16
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T16
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T9,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T3,T4,T16
0	0	1	-	-	Unreachable	T3,T32,T21
0	0	0	1	-	Covered	T3,T32,T21
0	0	0	0	1	Covered	T3,T4,T16
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	391034945	1168203	0	0
PostPackRule_A	391034945	12767	0	0
PrePackRule_A	391034945	6389	0	0
WidthCheck_A	1058	1058	0	0
u_state_regs_A	391034945	390227227	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	1168203	0	0
T3	384033	32768	0	0
T4	80192	34	0	0
T5	123953	0	0	0
T6	96800	56	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	2	0	0
T17	853	0	0	0
T18	0	168	0	0
T20	0	657	0	0
T32	0	433	0	0
T39	0	32	0	0
T44	0	1	0	0
T56	117038	0	0	0
T57	0	27	0	0
T59	1497	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	12767	0	0
T4	80192	23	0	0
T5	123953	0	0	0
T6	96800	0	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	2	0	0
T17	853	0	0	0
T18	0	5	0	0
T20	0	332	0	0
T21	0	1	0	0
T32	0	96	0	0
T39	0	15	0	0
T56	117038	0	0	0
T57	32358	21	0	0
T59	1497	0	0	0
T72	0	6	0	0
T187	0	21	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	6389	0	0
T4	80192	10	0	0
T5	123953	0	0	0
T6	96800	0	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	1	0	0
T17	853	0	0	0
T18	0	1	0	0
T20	0	125	0	0
T32	0	73	0	0
T39	0	12	0	0
T44	0	1	0	0
T56	117038	0	0	0
T57	32358	18	0	0
T59	1497	0	0	0
T72	0	7	0	0
T187	0	6	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391034945	390227227	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0