Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393999459	30725597	0	0
DepthKnown_A	393999459	393106710	0	0
RvalidKnown_A	393999459	393106710	0	0
WreadyKnown_A	393999459	393106710	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	30725597	0	0
T1	1164	204	0	0
T2	1877	136	0	0
T3	384033	222	0	0
T4	80192	8569	0	0
T5	123953	26465	0	0
T6	96800	42815	0	0
T7	121638	29631	0	0
T8	115499	38467	0	0
T16	4749	800	0	0
T17	853	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393999459	34056395	0	0
DepthKnown_A	393999459	393106710	0	0
RvalidKnown_A	393999459	393106710	0	0
WreadyKnown_A	393999459	393106710	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	34056395	0	0
T1	1164	204	0	0
T2	1877	136	0	0
T3	384033	966	0	0
T4	80192	26752	0	0
T5	123953	26465	0	0
T6	96800	42815	0	0
T7	121638	29631	0	0
T8	115499	38467	0	0
T16	4749	669	0	0
T17	853	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393999459	1767053	0	0
DepthKnown_A	393999459	393106710	0	0
RvalidKnown_A	393999459	393106710	0	0
WreadyKnown_A	393999459	393106710	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	1767053	0	0
T1	1164	3	0	0
T2	1877	0	0	0
T3	384033	0	0	0
T4	80192	1441	0	0
T5	123953	0	0	0
T6	96800	1186	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	142	0	0
T17	853	0	0	0
T18	0	10614	0	0
T32	0	6846	0	0
T39	0	237	0	0
T40	0	54	0	0
T44	0	7	0	0
T57	0	1245	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393999459	2226617	0	0
DepthKnown_A	393999459	393106710	0	0
RvalidKnown_A	393999459	393106710	0	0
WreadyKnown_A	393999459	393106710	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	2226617	0	0
T1	1164	3	0	0
T2	1877	0	0	0
T3	384033	0	0	0
T4	80192	4463	0	0
T5	123953	0	0	0
T6	96800	1186	0	0
T7	121638	0	0	0
T8	115499	0	0	0
T16	4749	19	0	0
T17	853	0	0	0
T18	0	10614	0	0
T32	0	6846	0	0
T39	0	147	0	0
T40	0	10	0	0
T44	0	39	0	0
T57	0	1245	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999459	393106710	0	0
T1	1164	1095	0	0
T2	1877	1814	0	0
T3	384033	384018	0	0
T4	80192	80127	0	0
T5	123953	123789	0	0
T6	96800	96706	0	0
T7	121638	121514	0	0
T8	115499	115353	0	0
T16	4749	4497	0	0
T17	853	803	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0