Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27292021	1		T1	11295		T2	154		T3	276
full_word	7799917	1		T1	4881		T2	3		T3	241

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35091638	1		T1	16176		T2	157		T3	517
auto[TlIntgErrCmd]	88	1		T51	1		T233	5		T256	5
auto[TlIntgErrData]	103	1		T51	5		T233	2		T256	11
auto[TlIntgErrBoth]	109	1		T51	4		T233	3		T256	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30582864	1		T1	10950		T2	149		T3	411
auto[1]	4509074	1		T1	5226		T2	8		T3	106

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26624949	1		T1	10949		T2	148		T3	255
auto[TlIntgErrNone]	partial	auto[1]	666798	1		T1	346		T2	6		T3	21
auto[TlIntgErrNone]	full_word	auto[0]	3957772	1		T1	1		T2	1		T3	156
auto[TlIntgErrNone]	full_word	auto[1]	3842119	1		T1	4880		T2	2		T3	85
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T233	1		T256	3		T274	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T51	1		T233	3		T256	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T342	1		T343	1		T348	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T233	1		T342	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1		T51	3		T233	1		T256	4
auto[TlIntgErrData]	partial	auto[1]	45	1		T51	2		T233	1		T256	4
auto[TlIntgErrData]	full_word	auto[0]	2	1		T256	1		T342	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1		T256	2		T271	3		T344	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T51	1		T233	1		T256	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T51	3		T233	2		T256	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T274	1		T341	1		T273	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T344	1		T343	1		T311	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23958	1		T51	9		T187	192		T188	49
full_word	4465647	1		T4	157		T5	16465		T6	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4489326	1		T4	157		T5	16465		T6	8
auto[TlIntgErrCmd]	86	1		T51	2		T233	2		T256	5
auto[TlIntgErrData]	104	1		T51	4		T233	5		T256	6
auto[TlIntgErrBoth]	89	1		T51	4		T233	2		T256	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4460070	1		T4	157		T5	16465		T6	8
auto[1]	29535	1		T51	6		T187	250		T188	65

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1447	1		T187	7		T188	4		T216	72
auto[TlIntgErrNone]	partial	auto[1]	22265	1		T187	185		T188	45		T216	1759
auto[TlIntgErrNone]	full_word	auto[0]	4458510	1		T4	157		T5	16465		T6	8
auto[TlIntgErrNone]	full_word	auto[1]	7104	1		T187	65		T188	20		T216	256
auto[TlIntgErrCmd]	partial	auto[0]	24	1		T51	1		T233	2		T256	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T51	1		T256	2		T274	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1		T344	1		T342	1		T345	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T256	1		T344	1		T345	2
auto[TlIntgErrData]	partial	auto[0]	43	1		T51	1		T233	3		T256	2
auto[TlIntgErrData]	partial	auto[1]	55	1		T51	3		T233	1		T256	4
auto[TlIntgErrData]	full_word	auto[0]	2	1		T271	1		T342	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T233	1		T343	1		T311	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T51	1		T256	5		T274	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T51	2		T233	2		T256	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T51	1		T271	1		T348	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T341	1		T344	1		T348	1