Module Definition
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Module : flash_phy_rd_buf_dep
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.48 100.00 89.91 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.59 100.00 90.37 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT4,T5,T6 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T28
11CoveredT4,T5,T6 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT4,T5,T28
10CoveredT1,T2,T3
11CoveredT4,T5,T6
Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T5,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T4,T5,T6
0 - 0 Covered T1,T2,T3

Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 820369286 7337837 0 0
BufferDepRsp_A 820369286 818740610 0 0
BufferIncrOverFlow_A 820369286 7337849 0 0
DepBufferRspOrder_A 820369288 16927347 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 820369286 7337837 0 0
T4 404122 189 0 0
T5 1790198 32065 0 0
T6 5688 76 0 0
T7 77826 19609 0 0
T11 251352 10240 0 0
T16 4248 84 0 0
T17 198216 29930 0 0
T18 0 15165 0 0
T19 1490322 26863 0 0
T27 712172 49896 0 0
T28 625282 49846 0 0
T38 0 2192 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 820369286 818740610 0 0
T1 66714 66552 0 0
T2 6386 5078 0 0
T3 2726 2550 0 0
T4 404122 403988 0 0
T5 1790198 1789942 0 0
T6 5688 5370 0 0
T7 77826 77696 0 0
T11 251352 251346 0 0
T16 4248 3996 0 0
T17 198216 197950 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 820369286 7337849 0 0
T4 404122 189 0 0
T5 1790198 32065 0 0
T6 5688 76 0 0
T7 77826 19609 0 0
T11 251352 10240 0 0
T16 4248 84 0 0
T17 198216 29930 0 0
T18 0 15165 0 0
T19 1490322 26863 0 0
T27 712172 49896 0 0
T28 625282 49846 0 0
T38 0 2192 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 820369288 16927347 0 0
T1 33357 32 0 0
T2 3193 100 0 0
T3 1363 32 0 0
T4 404122 221 0 0
T5 1790198 32106 0 0
T6 5688 140 0 0
T7 77826 19641 0 0
T11 251352 537696 0 0
T16 4248 148 0 0
T17 198216 29994 0 0
T18 0 15165 0 0
T19 745161 12672 0 0
T27 356086 24959 0 0
T28 312641 25768 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT4,T5,T16 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T16
110Not Covered
111CoveredT4,T5,T16 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T16
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T28
11CoveredT4,T5,T16 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T16
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT4,T5,T28
10CoveredT1,T2,T3
11CoveredT4,T5,T16
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T16 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T16 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T16
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T16
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T5,T16
0 0 - Covered T1,T2,T3
0 - 1 Covered T4,T5,T16
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 410184643 4544278 0 0
BufferDepRsp_A 410184643 409370305 0 0
BufferIncrOverFlow_A 410184643 4544283 0 0
DepBufferRspOrder_A 410184644 9620613 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184643 4544278 0 0
T4 202061 114 0 0
T5 895099 15206 0 0
T6 2844 0 0 0
T7 38913 10379 0 0
T11 125676 8192 0 0
T16 2124 84 0 0
T17 99108 15262 0 0
T19 745161 14191 0 0
T27 356086 24937 0 0
T28 312641 24078 0 0
T38 0 2192 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184643 409370305 0 0
T1 33357 33276 0 0
T2 3193 2539 0 0
T3 1363 1275 0 0
T4 202061 201994 0 0
T5 895099 894971 0 0
T6 2844 2685 0 0
T7 38913 38848 0 0
T11 125676 125673 0 0
T16 2124 1998 0 0
T17 99108 98975 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184643 4544283 0 0
T4 202061 114 0 0
T5 895099 15206 0 0
T6 2844 0 0 0
T7 38913 10379 0 0
T11 125676 8192 0 0
T16 2124 84 0 0
T17 99108 15262 0 0
T19 745161 14191 0 0
T27 356086 24937 0 0
T28 312641 24078 0 0
T38 0 2192 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184644 9620613 0 0
T1 33357 32 0 0
T2 3193 100 0 0
T3 1363 32 0 0
T4 202061 146 0 0
T5 895099 15247 0 0
T6 2844 64 0 0
T7 38913 10411 0 0
T11 125676 273504 0 0
T16 2124 148 0 0
T17 99108 15326 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT11,T54,T126
101CoveredT1,T2,T3
110Not Covered
111CoveredT4,T5,T6 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T28,T19
11CoveredT4,T5,T6 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT4,T28,T19
10CoveredT1,T2,T3
11CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T5,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T4,T5,T6
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 410184643 2793559 0 0
BufferDepRsp_A 410184643 409370305 0 0
BufferIncrOverFlow_A 410184643 2793566 0 0
DepBufferRspOrder_A 410184644 7306734 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184643 2793559 0 0
T4 202061 75 0 0
T5 895099 16859 0 0
T6 2844 76 0 0
T7 38913 9230 0 0
T11 125676 2048 0 0
T16 2124 0 0 0
T17 99108 14668 0 0
T18 0 15165 0 0
T19 745161 12672 0 0
T27 356086 24959 0 0
T28 312641 25768 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184643 409370305 0 0
T1 33357 33276 0 0
T2 3193 2539 0 0
T3 1363 1275 0 0
T4 202061 201994 0 0
T5 895099 894971 0 0
T6 2844 2685 0 0
T7 38913 38848 0 0
T11 125676 125673 0 0
T16 2124 1998 0 0
T17 99108 98975 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184643 2793566 0 0
T4 202061 75 0 0
T5 895099 16859 0 0
T6 2844 76 0 0
T7 38913 9230 0 0
T11 125676 2048 0 0
T16 2124 0 0 0
T17 99108 14668 0 0
T18 0 15165 0 0
T19 745161 12672 0 0
T27 356086 24959 0 0
T28 312641 25768 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410184644 7306734 0 0
T4 202061 75 0 0
T5 895099 16859 0 0
T6 2844 76 0 0
T7 38913 9230 0 0
T11 125676 264192 0 0
T16 2124 0 0 0
T17 99108 14668 0 0
T18 0 15165 0 0
T19 745161 12672 0 0
T27 356086 24959 0 0
T28 312641 25768 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%