Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1640738572	1637481220	0	0
CheckNGreaterZero_A	4252	4252	0	0
GntImpliesReady_A	1640738572	462576683	0	0
GntImpliesValid_A	1640738572	462576683	0	0
GrantKnown_A	1640738572	1637481220	0	0
IdxKnown_A	1640738572	1637481220	0	0
IndexIsCorrect_A	1640738572	462576683	0	0
NoReadyValidNoGrant_A	1640738572	179132915	0	0
Priority_A	1640738572	487077536	0	0
ReadyAndValidImplyGrant_A	1640738572	462576683	0	0
ReqAndReadyImplyGrant_A	1640738572	462576683	0	0
ReqImpliesValid_A	1640738572	487077536	0	0
ValidKnown_A	1640738572	1637481220	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	1637481220	0	0
T1	133428	133104	0	0
T2	12772	10156	0	0
T3	5452	5100	0	0
T4	808244	807976	0	0
T5	3580396	3579884	0	0
T6	11376	10740	0	0
T7	155652	155392	0	0
T11	502704	502692	0	0
T16	8496	7992	0	0
T17	396432	395900	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4252	4252	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	462576683	0	0
T1	133428	42372	0	0
T2	12772	212	0	0
T3	5452	64	0	0
T4	808244	397330	0	0
T5	3580396	64212	0	0
T6	11376	410	0	0
T7	155652	39282	0	0
T11	502704	1089042	0	0
T16	8496	1314	0	0
T17	396432	59988	0	0
T19	0	25344	0	0
T27	0	143652	0	0
T28	0	193402	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	462576683	0	0
T1	133428	42372	0	0
T2	12772	212	0	0
T3	5452	64	0	0
T4	808244	397330	0	0
T5	3580396	64212	0	0
T6	11376	410	0	0
T7	155652	39282	0	0
T11	502704	1089042	0	0
T16	8496	1314	0	0
T17	396432	59988	0	0
T19	0	25344	0	0
T27	0	143652	0	0
T28	0	193402	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	1637481220	0	0
T1	133428	133104	0	0
T2	12772	10156	0	0
T3	5452	5100	0	0
T4	808244	807976	0	0
T5	3580396	3579884	0	0
T6	11376	10740	0	0
T7	155652	155392	0	0
T11	502704	502692	0	0
T16	8496	7992	0	0
T17	396432	395900	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	1637481220	0	0
T1	133428	133104	0	0
T2	12772	10156	0	0
T3	5452	5100	0	0
T4	808244	807976	0	0
T5	3580396	3579884	0	0
T6	11376	10740	0	0
T7	155652	155392	0	0
T11	502704	502692	0	0
T16	8496	7992	0	0
T17	396432	395900	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	462576683	0	0
T1	133428	42372	0	0
T2	12772	212	0	0
T3	5452	64	0	0
T4	808244	397330	0	0
T5	3580396	64212	0	0
T6	11376	410	0	0
T7	155652	39282	0	0
T11	502704	1089042	0	0
T16	8496	1314	0	0
T17	396432	59988	0	0
T19	0	25344	0	0
T27	0	143652	0	0
T28	0	193402	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	179132915	0	0
T1	66714	256	0	0
T2	6386	796	0	0
T3	2726	256	0	0
T4	808244	1510	0	0
T5	3580396	2116118	0	0
T6	11376	952	0	0
T7	155652	51244	0	0
T11	502704	425034	0	0
T16	8496	992	0	0
T17	396432	162280	0	0
T18	0	82332	0	0
T19	1490322	875504	0	0
T27	712172	179236	0	0
T28	625282	92522	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	487077536	0	0
T1	133428	42372	0	0
T2	12772	212	0	0
T3	5452	64	0	0
T4	808244	397436	0	0
T5	3580396	494980	0	0
T6	11376	410	0	0
T7	155652	49168	0	0
T11	502704	1089042	0	0
T16	8496	1314	0	0
T17	396432	62858	0	0
T19	0	256154	0	0
T27	0	174494	0	0
T28	0	245034	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	462576683	0	0
T1	133428	42372	0	0
T2	12772	212	0	0
T3	5452	64	0	0
T4	808244	397330	0	0
T5	3580396	64212	0	0
T6	11376	410	0	0
T7	155652	39282	0	0
T11	502704	1089042	0	0
T16	8496	1314	0	0
T17	396432	59988	0	0
T19	0	25344	0	0
T27	0	143652	0	0
T28	0	193402	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	462576683	0	0
T1	133428	42372	0	0
T2	12772	212	0	0
T3	5452	64	0	0
T4	808244	397330	0	0
T5	3580396	64212	0	0
T6	11376	410	0	0
T7	155652	39282	0	0
T11	502704	1089042	0	0
T16	8496	1314	0	0
T17	396432	59988	0	0
T19	0	25344	0	0
T27	0	143652	0	0
T28	0	193402	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	487077536	0	0
T1	133428	42372	0	0
T2	12772	212	0	0
T3	5452	64	0	0
T4	808244	397436	0	0
T5	3580396	494980	0	0
T6	11376	410	0	0
T7	155652	49168	0	0
T11	502704	1089042	0	0
T16	8496	1314	0	0
T17	396432	62858	0	0
T19	0	256154	0	0
T27	0	174494	0	0
T28	0	245034	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1640738572	1637481220	0	0
T1	133428	133104	0	0
T2	12772	10156	0	0
T3	5452	5100	0	0
T4	808244	807976	0	0
T5	3580396	3579884	0	0
T6	11376	10740	0	0
T7	155652	155392	0	0
T11	502704	502692	0	0
T16	8496	7992	0	0
T17	396432	395900	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410184643	409370305	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	410184643	131847840	0	0
GntImpliesValid_A	410184643	131847840	0	0
GrantKnown_A	410184643	409370305	0	0
IdxKnown_A	410184643	409370305	0	0
IndexIsCorrect_A	410184643	131847840	0	0
NoReadyValidNoGrant_A	410184643	47481346	0	0
Priority_A	410184643	138128270	0	0
ReadyAndValidImplyGrant_A	410184643	131847840	0	0
ReqAndReadyImplyGrant_A	410184643	131847840	0	0
ReqImpliesValid_A	410184643	138128270	0	0
ValidKnown_A	410184643	409370305	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131847840	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131847840	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131847840	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	47481346	0	0
T1	33357	128	0	0
T2	3193	398	0	0
T3	1363	128	0	0
T4	202061	638	0	0
T5	895099	502865	0	0
T6	2844	256	0	0
T7	38913	13688	0	0
T11	125676	107353	0	0
T16	2124	496	0	0
T17	99108	41235	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	138128270	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132458	0	0
T5	895099	138791	0	0
T6	2844	64	0	0
T7	38913	13109	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15977	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131847840	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131847840	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	138128270	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132458	0	0
T5	895099	138791	0	0
T6	2844	64	0	0
T7	38913	13109	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15977	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410184643	409370305	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	410184643	131644945	0	0
GntImpliesValid_A	410184643	131644945	0	0
GrantKnown_A	410184643	409370305	0	0
IdxKnown_A	410184643	409370305	0	0
IndexIsCorrect_A	410184643	131644945	0	0
NoReadyValidNoGrant_A	410184643	47481347	0	0
Priority_A	410184643	137925374	0	0
ReadyAndValidImplyGrant_A	410184643	131644945	0	0
ReqAndReadyImplyGrant_A	410184643	131644945	0	0
ReqImpliesValid_A	410184643	137925374	0	0
ValidKnown_A	410184643	409370305	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131644945	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131644945	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131644945	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	47481347	0	0
T1	33357	128	0	0
T2	3193	398	0	0
T3	1363	128	0	0
T4	202061	638	0	0
T5	895099	502865	0	0
T6	2844	256	0	0
T7	38913	13688	0	0
T11	125676	107353	0	0
T16	2124	496	0	0
T17	99108	41235	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	137925374	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132458	0	0
T5	895099	138791	0	0
T6	2844	64	0	0
T7	38913	13109	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15977	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131644945	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	131644945	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132405	0	0
T5	895099	15247	0	0
T6	2844	64	0	0
T7	38913	10411	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15326	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	137925374	0	0
T1	33357	11978	0	0
T2	3193	106	0	0
T3	1363	32	0	0
T4	202061	132458	0	0
T5	895099	138791	0	0
T6	2844	64	0	0
T7	38913	13109	0	0
T11	125676	274908	0	0
T16	2124	657	0	0
T17	99108	15977	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T17
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T17
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410184643	409370305	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	410184643	99541949	0	0
GntImpliesValid_A	410184643	99541949	0	0
GrantKnown_A	410184643	409370305	0	0
IdxKnown_A	410184643	409370305	0	0
IndexIsCorrect_A	410184643	99541949	0	0
NoReadyValidNoGrant_A	410184643	42085111	0	0
Priority_A	410184643	105511946	0	0
ReadyAndValidImplyGrant_A	410184643	99541949	0	0
ReqAndReadyImplyGrant_A	410184643	99541949	0	0
ReqImpliesValid_A	410184643	105511946	0	0
ValidKnown_A	410184643	409370305	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	42085111	0	0
T4	202061	117	0	0
T5	895099	555194	0	0
T6	2844	220	0	0
T7	38913	11934	0	0
T11	125676	105164	0	0
T16	2124	0	0	0
T17	99108	39905	0	0
T18	0	41166	0	0
T19	745161	437752	0	0
T27	356086	89618	0	0
T28	312641	46261	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	105511946	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	108699	0	0
T6	2844	141	0	0
T7	38913	11475	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	15452	0	0
T19	0	128077	0	0
T27	0	87247	0	0
T28	0	122517	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	105511946	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	108699	0	0
T6	2844	141	0	0
T7	38913	11475	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	15452	0	0
T19	0	128077	0	0
T27	0	87247	0	0
T28	0	122517	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T17
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T17
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410184643	409370305	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	410184643	99541949	0	0
GntImpliesValid_A	410184643	99541949	0	0
GrantKnown_A	410184643	409370305	0	0
IdxKnown_A	410184643	409370305	0	0
IndexIsCorrect_A	410184643	99541949	0	0
NoReadyValidNoGrant_A	410184643	42085111	0	0
Priority_A	410184643	105511946	0	0
ReadyAndValidImplyGrant_A	410184643	99541949	0	0
ReqAndReadyImplyGrant_A	410184643	99541949	0	0
ReqImpliesValid_A	410184643	105511946	0	0
ValidKnown_A	410184643	409370305	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	42085111	0	0
T4	202061	117	0	0
T5	895099	555194	0	0
T6	2844	220	0	0
T7	38913	11934	0	0
T11	125676	105164	0	0
T16	2124	0	0	0
T17	99108	39905	0	0
T18	0	41166	0	0
T19	745161	437752	0	0
T27	356086	89618	0	0
T28	312641	46261	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	105511946	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	108699	0	0
T6	2844	141	0	0
T7	38913	11475	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	15452	0	0
T19	0	128077	0	0
T27	0	87247	0	0
T28	0	122517	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	99541949	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	16859	0	0
T6	2844	141	0	0
T7	38913	9230	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	14668	0	0
T19	0	12672	0	0
T27	0	71826	0	0
T28	0	96701	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	105511946	0	0
T1	33357	9208	0	0
T2	3193	0	0	0
T3	1363	0	0	0
T4	202061	66260	0	0
T5	895099	108699	0	0
T6	2844	141	0	0
T7	38913	11475	0	0
T11	125676	269613	0	0
T16	2124	0	0	0
T17	99108	15452	0	0
T19	0	128077	0	0
T27	0	87247	0	0
T28	0	122517	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410184643	409370305	0	0
T1	33357	33276	0	0
T2	3193	2539	0	0
T3	1363	1275	0	0
T4	202061	201994	0	0
T5	895099	894971	0	0
T6	2844	2685	0	0
T7	38913	38848	0	0
T11	125676	125673	0	0
T16	2124	1998	0	0
T17	99108	98975	0	0