Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	390967	1		T1	2		T2	2		T3	2
all_values[1]	390967	1		T1	2		T2	2		T3	2
all_values[2]	390967	1		T1	2		T2	2		T3	2
all_values[3]	390967	1		T1	2		T2	2		T3	2
all_values[4]	390967	1		T1	2		T2	2		T3	2
all_values[5]	390967	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	788324	1		T1	12		T2	12		T3	12
auto[1]	1557478	1		T6	11204		T7	30356		T34	94512

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1146332	1		T1	7		T2	7		T3	7
auto[1]	1199470	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	390809	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	158	1		T258	3		T259	2		T260	3
all_values[1]	auto[0]	auto[1]	390798	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	169	1		T258	3		T260	5		T320	5
all_values[2]	auto[0]	auto[0]	1627	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	46	1		T259	1		T320	2		T323	2
all_values[2]	auto[1]	auto[0]	389233	1		T6	2801		T7	7589		T34	23628
all_values[2]	auto[1]	auto[1]	61	1		T259	2		T320	1		T321	2
all_values[3]	auto[0]	auto[0]	1634	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	60	1		T331	2		T258	1		T320	1
all_values[3]	auto[1]	auto[0]	72127	1		T6	931		T7	81		T23	936
all_values[3]	auto[1]	auto[1]	317146	1		T6	1870		T7	7508		T34	23628
all_values[4]	auto[0]	auto[0]	1140	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	531	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	289822	1		T6	1866		T7	6441		T34	22688
all_values[4]	auto[1]	auto[1]	99474	1		T6	935		T7	1148		T34	940
all_values[5]	auto[0]	auto[0]	1541	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	138	1		T35	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	389208	1		T6	2801		T7	7589		T34	23628
all_values[5]	auto[1]	auto[1]	80	1		T260	2		T320	3		T321	3