---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.PrimRspPayLoad_A	0	0	443449232	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	443449232	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	443449232	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	443449232	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	443449232	0	0	0
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	443449232	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	443449232	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	443449232	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	443449232	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	443449232	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	443449232	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1062	1062	0	0
tb.dut.FlashAddrKnown_A	0	0	443449232	307305959	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.FlashKnownO_A	0	0	443449232	442636052	0	0
tb.dut.FlashProgKnown_A	0	0	443449232	189746767	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	443449232	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	443449232	50	0	0
tb.dut.IntrErrO_A	0	0	443449232	442636052	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	443449232	442636052	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	443449232	442636052	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	443449232	442636052	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	443449232	442636052	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	443449232	442636052	0	0
tb.dut.MemRspPayLoad_A	0	0	443449232	5727090	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	443449232	442636052	0	0
tb.dut.MemTlDValidKnownO_A	0	0	443449232	442636052	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	443449232	442636052	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	443449232	442636052	0	0
tb.dut.RspPayLoad_A	0	0	442944831	43919778	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.TdoEnIsOne_A	0	0	443449232	442636052	0	0
tb.dut.TdoKnown_A	0	0	443449232	442636052	0	0
tb.dut.TlAReadyKnownO_A	0	0	443449232	442636052	0	0
tb.dut.TlDValidKnownO_A	0	0	443449232	442636052	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	445986946	3536	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	445986946	1795	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	445986946	2508	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	445986946	3197	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	445986946	3223	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	445986946	2631	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	445986946	3104	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	445986946	2702	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	445986946	2749	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	445986946	2380	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	445986946	3218	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	445986946	3128	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	445986946	1873	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	445986946	2000	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	445986946	1965	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	445986946	1967	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	445986946	1469	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	445986946	2008	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	445986946	2056	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	445986946	1882	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	445986946	1917	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	445986946	1386	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	445986946	2433	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	445986946	1919	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	445986946	2630	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	445986946	2308	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	445986946	2055	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	445986946	1457	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	445986946	2381	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	445986946	2573	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	445986946	3162	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	445986946	3027	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	445986946	3000	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	445986946	3387	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	445986946	3193	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	445986946	2663	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	445986946	2068	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	445986946	2792	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	445986946	1164	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	445986946	1856	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	445986946	1552	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	445986946	1604	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	445986946	1716	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	445986946	1596	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	445986946	1134	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	445986946	1969	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	445986946	1787	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	445986946	2018	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	445986946	2730	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	445986946	2021	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	445986946	2340	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	445986946	2338	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	445986946	1987	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	445986946	2070	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	445986946	1523	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	445986946	2416	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	445986946	927	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	445986946	2125	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	445986946	1456	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	445986946	2087	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	445986946	2406	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	445986946	1779	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	445986946	1475	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	445986946	1863	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	445986946	1711	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	445986946	1708	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	445986946	2208	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	445986946	1877	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	445986946	1721	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	445986946	2911	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	445986946	3178	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	445986946	2659	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	445986946	3350	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	445986946	2547	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	445986946	3149	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	445986946	2729	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	445986946	2603	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	445986946	1142	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	445986946	970	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	445986946	2007	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	445986946	1369	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	445986946	2094	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	445986946	1535	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	445986946	2003	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	445986946	1948	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	445986946	2052	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	445986946	1994	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	443449232	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	443449232	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	443449232	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	443449232	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	443449232	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	443449232	28	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	445986925	36027309	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	445986925	445090866	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	445986925	44683036	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	445986925	445090866	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
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tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1272	1272	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	445987611	4945936	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	445986925	6151	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	445987611	33332954	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	445483210	37398838	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	445986925	4732	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	445987611	36027312	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	445987611	44683050	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	445987611	36027312	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	445987611	44683050	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	445987611	44683050	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	445987611	44683050	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	445986925	4744	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	445986925	5152	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1277	1277	0	0
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_ctrl_arb.u_state_regs_A	0	0	443449253	442636073	0	0
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_disable_buf.OutputsKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A	0	0	443449232	2251588	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A	0	0	443449232	2251574	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A	0	0	443449232	23586304	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	443449232	1241956	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	443449232	17129	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	443449232	8757	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	443449232	129798979	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	443449232	129798979	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	443449232	129798979	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	443449232	47456733	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	443449232	136019081	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	443449232	129798979	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	443449232	129798979	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	443449232	136019081	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	443449232	129670145	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	443449232	129670145	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	443449232	129670145	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	443449232	47456736	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	443449232	135890244	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	443449232	129670145	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	443449232	129670145	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	443449232	135890244	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A	0	0	443449232	1236644	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A	0	0	443449232	2648662	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A	0	0	443449232	54525241	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	443449232	826608	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	443449232	826607	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	443449232	826219	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	443449232	826216	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	443449232	826178	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	443449232	826177	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	443449232	825814	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	443449232	825813	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	443449232	12521009	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	12521009	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	443449232	4541457	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	443449232	4541463	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	443449234	9693547	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	442944831	14251571	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	442944831	14251571	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	442944831	54520987	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	442944831	54520987	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	443449232	3263725	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	443449232	3263725	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	443449232	3263725	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	443449232	317980648	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	443449232	3263725	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	443449232	3263725	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	443449232	119416847	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	443449232	30905	0	1057
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A	0	0	442944831	3293871	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	442944831	3293871	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A	0	0	443449232	2147172	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A	0	0	443449232	2147172	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A	0	0	443449232	22416677	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	443449232	1160910	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	443449232	13002	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	443449232	6367	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	443449232	42205791	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	443449232	106880832	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	443449232	106880832	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	443449232	42205791	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	443449232	106880832	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	443449232	100718114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	443449232	106880832	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A	0	0	443449232	371227	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A	0	0	443449232	1656588	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A	0	0	443449232	49236152	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	443449232	611340	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	443449232	611339	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	443449232	610946	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	443449232	610944	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	443449232	610905	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	443449232	610905	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	443449232	610185	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	443449232	610185	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	443449232	11013412	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	11013412	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	443449232	2814600	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	443449232	2814603	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	443449233	7325234	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	442944831	12238758	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	442944831	12238758	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	442944831	49230562	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	442944831	49230562	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	443449232	2445718	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	443449232	2445718	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	443449232	2445718	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	443449232	336680293	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	443449232	2445718	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	443449232	2445718	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	443449232	101409598	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	443449232	26168	0	1057
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A	0	0	442944831	2829349	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A	0	0	442944831	442131651	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	442944831	2829349	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A	0	0	443449232	34605431	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	34605431	0	0
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	21353650	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	5307436	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	5904454	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	443449232	117426388	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	117426388	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	78032146	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	7233176	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	6488064	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	6498462	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	443449232	85153887	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	85153887	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	443449232	65833574	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit	0	0	445986925	55460	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv	0	0	445986925	55460	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse	0	0	445986925	36396	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1277	1277	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse	0	0	445986925	19064	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A	0	0	437361632	436548452	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	437361632	436516334	0	2781
tb.dut.u_flash_hw_if.DisableChk_A	0	0	431156517	6722524	0	45
tb.dut.u_flash_hw_if.ProgRdVerify_A	0	0	429268096	2043549	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq	0	0	443449253	8961	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq	0	0	443353924	8630	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq	0	0	443449253	8927	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq	0	0	427902439	8628	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs_A	0	0	443449253	442636073	0	0
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_flash_hw_if.u_state_regs_A	0	0	443449253	442636073	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	437361653	436548473	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_flash_mp.BankEraseData_A	0	0	443449253	7603857	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	443449253	11731660	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	443449253	272587815	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	443449253	307417745	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	443449253	34829930	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	437150856	111742	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	443449253	19335517	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	443449253	154907732	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	443449253	307305968	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	443449253	307305968	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	1062	1062	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	1062	1062	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	1062	1062	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	1062	1062	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	1062	1062	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	1062	1062	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	437338438	436525258	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	437338438	436493275	0	2631
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	437361653	436548473	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_prog_fifo.DataKnown_A	0	0	443449232	196882704	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	196882704	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	437361632	436548452	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	437361632	436548452	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	443449232	442636052	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1062	1062	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1062	1062	0	0
tb.dut.u_reg_core.en2addrHit	0	0	445986946	29002432	0	0
tb.dut.u_reg_core.reAfterRv	0	0	445986946	29002414	0	0
tb.dut.u_reg_core.rePulse	0	0	445986946	26580433	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	445986946	445090887	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	445986946	445090887	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	445986925	36027309	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	445986925	44683036	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	445986925	2416422	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	445986925	3628221	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	445986925	4137518	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	445986925	4877555	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	445986925	29403480	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	445986925	36177260	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	445986925	445090866	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1277	1277	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1277	1277	0	0
tb.dut.u_reg_core.wePulse	0	0	445986946	2421981	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	443449253	442636073	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	437361653	436548473	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	437361653	436548473	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	437361653	436548473	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	437361653	436548473	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	443449232	49268666	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	49268666	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_A	0	0	443449232	5726954	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	443449232	4597741	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	443449232	4597741	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	443449232	35734310	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	35734310	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1062	1062	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	443449232	5718158	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	5718158	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	443449232	34605431	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	34605431	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1062	1062	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	437361632	436548452	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	437361632	436548452	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1062	1062	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	443449232	442636052	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1062	1062	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.TlOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A	0	0	443449232	3584766	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	443449232	3584766	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	3584766	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1062	1062	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1062	1062	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1062	1062	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1062	1062	0	0
tb.dut.u_to_rd_fifo.TlOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A	0	0	443449232	4873757	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1062	1062	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	443449232	3285808	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	442315746	3279335	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1062	1062	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	443449232	4873757	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	4873757	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1062	1062	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1062	1062	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	442944831	4859907	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	4878413	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	443449232	3285808	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	443449232	442636052	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	443449232	3285808	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	443449232	30905	0	1057
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	443449232	26168	0	1057
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	437361632	436516334	0	2781
tb.dut.u_flash_hw_if.DisableChk_A	0	0	431156517	6722524	0	45
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	437338438	436493275	0	2631
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	437361653	436516340	0	2781

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	445987611	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	445987611	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	445987611	99710	99710	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	445987611	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	445987611	22	22	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	445987611	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	445987611	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	445987611	16603	16603	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	445987611	281459	281459	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	445987611	20750462	20750462	1252

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	445987611	99710	99710	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	445987611	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	445987611	22	22	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	445987611	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	445987611	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	445987611	16603	16603	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	445987611	281459	281459	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	445987611	20750462	20750462	1252