Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
231 | 
1 | 
 | 
T17 | 
14 | 
 | 
T18 | 
9 | 
 | 
T21 | 
11 | 
| others[1] | 
210 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
8 | 
 | 
T21 | 
10 | 
| others[2] | 
211 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
11 | 
 | 
T21 | 
7 | 
| others[3] | 
387 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
20 | 
 | 
T21 | 
17 | 
| false | 
115 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
6 | 
 | 
T21 | 
9 | 
| true | 
12705 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8224 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
17 | 
 | 
T18 | 
25 | 
| others[1] | 
1256 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
19 | 
 | 
T18 | 
18 | 
| others[2] | 
1270 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
29 | 
 | 
T18 | 
23 | 
| others[3] | 
2049 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
27 | 
 | 
T18 | 
24 | 
| false | 
621 | 
1 | 
 | 
T3 | 
1 | 
 | 
T16 | 
1 | 
 | 
T17 | 
9 | 
| true | 
439 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8203 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
19 | 
 | 
T6 | 
1 | 
| others[1] | 
1249 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
24 | 
 | 
T18 | 
21 | 
| others[2] | 
1250 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
16 | 
 | 
T18 | 
13 | 
| others[3] | 
2050 | 
1 | 
 | 
T3 | 
2 | 
 | 
T4 | 
1 | 
 | 
T16 | 
1 | 
| false | 
675 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
5 | 
 | 
T18 | 
9 | 
| true | 
432 | 
1 | 
 | 
T2 | 
1 | 
 | 
T19 | 
1 | 
 | 
T11 | 
2 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
103 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
5 | 
 | 
T21 | 
7 | 
| others[1] | 
102 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
4 | 
| others[2] | 
88 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
3 | 
 | 
T21 | 
3 | 
| others[3] | 
183 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
2 | 
 | 
T21 | 
8 | 
| false | 
54 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
3 | 
 | 
T21 | 
1 | 
| true | 
13329 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
237 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
8 | 
 | 
T7 | 
1 | 
| others[1] | 
236 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
12 | 
 | 
T21 | 
6 | 
| others[2] | 
242 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
9 | 
 | 
T21 | 
11 | 
| others[3] | 
388 | 
1 | 
 | 
T17 | 
19 | 
 | 
T18 | 
18 | 
 | 
T19 | 
1 | 
| false | 
108 | 
1 | 
 | 
T17 | 
1 | 
 | 
T18 | 
1 | 
 | 
T21 | 
3 | 
| true | 
12648 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8028 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
18 | 
 | 
T18 | 
22 | 
| others[1] | 
1091 | 
1 | 
 | 
T3 | 
1 | 
 | 
T16 | 
1 | 
 | 
T17 | 
26 | 
| others[2] | 
1101 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
18 | 
 | 
T18 | 
15 | 
| others[3] | 
1700 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
27 | 
 | 
T18 | 
32 | 
| false | 
547 | 
1 | 
 | 
T3 | 
2 | 
 | 
T4 | 
1 | 
 | 
T17 | 
12 | 
| true | 
1392 | 
1 | 
 | 
T2 | 
1 | 
 | 
T6 | 
1 | 
 | 
T19 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
206 | 
1 | 
 | 
T17 | 
6 | 
 | 
T6 | 
1 | 
 | 
T18 | 
14 | 
| others[1] | 
235 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
7 | 
 | 
T21 | 
12 | 
| others[2] | 
216 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
14 | 
 | 
T21 | 
8 | 
| others[3] | 
385 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
15 | 
 | 
T21 | 
17 | 
| false | 
122 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
7 | 
 | 
T21 | 
7 | 
| true | 
12695 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
211 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
10 | 
 | 
T21 | 
9 | 
| others[1] | 
210 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
8 | 
 | 
T21 | 
7 | 
| others[2] | 
230 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
7 | 
 | 
T21 | 
10 | 
| others[3] | 
350 | 
1 | 
 | 
T17 | 
19 | 
 | 
T18 | 
12 | 
 | 
T21 | 
20 | 
| false | 
107 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
4 | 
 | 
T21 | 
5 | 
| true | 
12751 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8200 | 
1 | 
 | 
T17 | 
15 | 
 | 
T18 | 
21 | 
 | 
T22 | 
4 | 
| others[1] | 
1269 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
27 | 
 | 
T18 | 
24 | 
| others[2] | 
1220 | 
1 | 
 | 
T3 | 
3 | 
 | 
T16 | 
1 | 
 | 
T17 | 
21 | 
| others[3] | 
2050 | 
1 | 
 | 
T3 | 
8 | 
 | 
T17 | 
29 | 
 | 
T18 | 
34 | 
| false | 
672 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
7 | 
| true | 
448 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1258 | 
1 | 
 | 
T3 | 
4 | 
 | 
T16 | 
1 | 
 | 
T17 | 
22 | 
| others[1] | 
1235 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
19 | 
 | 
T18 | 
21 | 
| others[2] | 
1243 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
13 | 
 | 
T18 | 
13 | 
| others[3] | 
2052 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
38 | 
 | 
T6 | 
1 | 
| false | 
663 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
9 | 
 | 
T18 | 
15 | 
| true | 
432 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T19 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
109 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
4 | 
 | 
T21 | 
6 | 
| others[1] | 
90 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
6 | 
 | 
T21 | 
1 | 
| others[2] | 
103 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
1 | 
 | 
T21 | 
6 | 
| others[3] | 
181 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
11 | 
 | 
T21 | 
11 | 
| false | 
50 | 
1 | 
 | 
T17 | 
1 | 
 | 
T18 | 
6 | 
 | 
T40 | 
1 | 
| true | 
6350 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
228 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
8 | 
| others[1] | 
251 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
18 | 
 | 
T21 | 
14 | 
| others[2] | 
259 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
8 | 
 | 
T21 | 
6 | 
| others[3] | 
373 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
18 | 
 | 
T21 | 
14 | 
| false | 
127 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
5 | 
 | 
T21 | 
7 | 
| true | 
5645 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1009 | 
1 | 
 | 
T3 | 
5 | 
 | 
T17 | 
19 | 
 | 
T18 | 
20 | 
| others[1] | 
1051 | 
1 | 
 | 
T3 | 
1 | 
 | 
T16 | 
1 | 
 | 
T17 | 
16 | 
| others[2] | 
1007 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
22 | 
 | 
T18 | 
15 | 
| others[3] | 
1871 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
34 | 
| false | 
586 | 
1 | 
 | 
T3 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
10 | 
| true | 
1359 | 
1 | 
 | 
T6 | 
1 | 
 | 
T12 | 
1 | 
 | 
T226 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
234 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
5 | 
 | 
T21 | 
9 | 
| others[1] | 
218 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
8 | 
 | 
T21 | 
13 | 
| others[2] | 
213 | 
1 | 
 | 
T17 | 
16 | 
 | 
T18 | 
12 | 
 | 
T21 | 
7 | 
| others[3] | 
409 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
18 | 
 | 
T18 | 
10 | 
| false | 
110 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
10 | 
 | 
T19 | 
1 | 
| true | 
5699 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
210 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
8 | 
 | 
T21 | 
10 | 
| others[1] | 
223 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
16 | 
 | 
T21 | 
8 | 
| others[2] | 
225 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
10 | 
| others[3] | 
348 | 
1 | 
 | 
T17 | 
14 | 
 | 
T18 | 
14 | 
 | 
T21 | 
13 | 
| false | 
123 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
5 | 
 | 
T21 | 
10 | 
| true | 
5754 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1205 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
20 | 
 | 
T18 | 
24 | 
| others[1] | 
1251 | 
1 | 
 | 
T3 | 
1 | 
 | 
T16 | 
1 | 
 | 
T17 | 
21 | 
| others[2] | 
1222 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
22 | 
 | 
T18 | 
22 | 
| others[3] | 
2119 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
31 | 
 | 
T18 | 
28 | 
| false | 
644 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
7 | 
 | 
T18 | 
7 | 
| true | 
442 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1288 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
21 | 
 | 
T18 | 
15 | 
| others[1] | 
1232 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
23 | 
| others[2] | 
1240 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
16 | 
 | 
T18 | 
20 | 
| others[3] | 
2060 | 
1 | 
 | 
T3 | 
7 | 
 | 
T16 | 
1 | 
 | 
T17 | 
35 | 
| false | 
631 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
6 | 
 | 
T22 | 
5 | 
| true | 
432 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
97 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
5 | 
 | 
T21 | 
2 | 
| others[1] | 
90 | 
1 | 
 | 
T17 | 
1 | 
 | 
T18 | 
4 | 
 | 
T21 | 
3 | 
| others[2] | 
93 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
3 | 
 | 
T21 | 
2 | 
| others[3] | 
178 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
10 | 
 | 
T21 | 
7 | 
| false | 
50 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
3 | 
 | 
T21 | 
2 | 
| true | 
6375 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
263 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
11 | 
 | 
T21 | 
12 | 
| others[1] | 
211 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
10 | 
 | 
T21 | 
10 | 
| others[2] | 
249 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
12 | 
 | 
T21 | 
11 | 
| others[3] | 
388 | 
1 | 
 | 
T17 | 
14 | 
 | 
T18 | 
20 | 
 | 
T7 | 
1 | 
| false | 
124 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
7 | 
 | 
T21 | 
6 | 
| true | 
5648 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
964 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
13 | 
| others[1] | 
1065 | 
1 | 
 | 
T3 | 
2 | 
 | 
T16 | 
1 | 
 | 
T17 | 
24 | 
| others[2] | 
1079 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
16 | 
| others[3] | 
1829 | 
1 | 
 | 
T3 | 
6 | 
 | 
T4 | 
1 | 
 | 
T17 | 
31 | 
| false | 
564 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
14 | 
| true | 
1382 | 
1 | 
 | 
T19 | 
1 | 
 | 
T11 | 
2 | 
 | 
T12 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
219 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
8 | 
 | 
T21 | 
6 | 
| others[1] | 
232 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
10 | 
 | 
T7 | 
1 | 
| others[2] | 
238 | 
1 | 
 | 
T17 | 
15 | 
 | 
T18 | 
5 | 
 | 
T21 | 
12 | 
| others[3] | 
410 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
12 | 
 | 
T6 | 
1 | 
| false | 
116 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
3 | 
 | 
T21 | 
6 | 
| true | 
5668 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
217 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
10 | 
 | 
T21 | 
7 | 
| others[1] | 
241 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
10 | 
 | 
T21 | 
9 | 
| others[2] | 
208 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
9 | 
 | 
T21 | 
12 | 
| others[3] | 
385 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
17 | 
| false | 
105 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
7 | 
 | 
T21 | 
6 | 
| true | 
5727 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1240 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
11 | 
 | 
T18 | 
21 | 
| others[1] | 
1192 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
18 | 
 | 
T18 | 
18 | 
| others[2] | 
1275 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
25 | 
 | 
T18 | 
25 | 
| others[3] | 
2072 | 
1 | 
 | 
T3 | 
2 | 
 | 
T16 | 
1 | 
 | 
T17 | 
38 | 
| false | 
669 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
9 | 
 | 
T18 | 
11 | 
| true | 
435 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1289 | 
1 | 
 | 
T3 | 
5 | 
 | 
T16 | 
1 | 
 | 
T17 | 
18 | 
| others[1] | 
1214 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
24 | 
 | 
T18 | 
22 | 
| others[2] | 
1296 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
16 | 
 | 
T18 | 
19 | 
| others[3] | 
2007 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
33 | 
 | 
T18 | 
39 | 
| false | 
658 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
10 | 
 | 
T6 | 
1 | 
| true | 
419 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T19 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
89 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
3 | 
 | 
T21 | 
4 | 
| others[1] | 
112 | 
1 | 
 | 
T17 | 
1 | 
 | 
T18 | 
5 | 
 | 
T21 | 
3 | 
| others[2] | 
107 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
7 | 
 | 
T21 | 
1 | 
| others[3] | 
182 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
11 | 
 | 
T21 | 
7 | 
| false | 
62 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
2 | 
 | 
T21 | 
2 | 
| true | 
6331 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
237 | 
1 | 
 | 
T17 | 
12 | 
 | 
T6 | 
1 | 
 | 
T18 | 
8 | 
| others[1] | 
241 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
15 | 
 | 
T7 | 
1 | 
| others[2] | 
219 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
11 | 
 | 
T21 | 
9 | 
| others[3] | 
381 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
13 | 
 | 
T21 | 
20 | 
| false | 
122 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
4 | 
 | 
T75 | 
12 | 
| true | 
5683 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1088 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
25 | 
 | 
T18 | 
23 | 
| others[1] | 
1040 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
26 | 
 | 
T11 | 
1 | 
| others[2] | 
1044 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
21 | 
 | 
T18 | 
14 | 
| others[3] | 
1761 | 
1 | 
 | 
T3 | 
8 | 
 | 
T16 | 
1 | 
 | 
T17 | 
28 | 
| false | 
575 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
9 | 
| true | 
1375 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
247 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
15 | 
 | 
T21 | 
14 | 
| others[1] | 
234 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
9 | 
 | 
T21 | 
8 | 
| others[2] | 
232 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
7 | 
 | 
T21 | 
12 | 
| others[3] | 
355 | 
1 | 
 | 
T17 | 
13 | 
 | 
T6 | 
1 | 
 | 
T18 | 
16 | 
| false | 
105 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
4 | 
 | 
T21 | 
8 | 
| true | 
5710 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
223 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
7 | 
 | 
T21 | 
9 | 
| others[1] | 
218 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
8 | 
 | 
T21 | 
8 | 
| others[2] | 
218 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
14 | 
 | 
T21 | 
6 | 
| others[3] | 
346 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
18 | 
 | 
T21 | 
21 | 
| false | 
112 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
6 | 
 | 
T21 | 
6 | 
| true | 
5766 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1239 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
25 | 
 | 
T18 | 
22 | 
| others[1] | 
1221 | 
1 | 
 | 
T3 | 
4 | 
 | 
T16 | 
1 | 
 | 
T17 | 
17 | 
| others[2] | 
1249 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
18 | 
 | 
T18 | 
13 | 
| others[3] | 
2068 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
30 | 
 | 
T18 | 
32 | 
| false | 
663 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
11 | 
| true | 
443 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1213 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
17 | 
 | 
T18 | 
17 | 
| others[1] | 
1193 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
27 | 
 | 
T18 | 
18 | 
| others[2] | 
1298 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
14 | 
 | 
T18 | 
26 | 
| others[3] | 
2113 | 
1 | 
 | 
T3 | 
6 | 
 | 
T17 | 
39 | 
 | 
T18 | 
26 | 
| false | 
628 | 
1 | 
 | 
T3 | 
1 | 
 | 
T16 | 
1 | 
 | 
T17 | 
4 | 
| true | 
438 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
 
 
| 0% | 
10% | 
20% | 
30% | 
40% | 
50% | 
60% | 
70% | 
80% | 
90% | 
100% |