Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
107 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
3 | 
 | 
T21 | 
5 | 
| others[1] | 
105 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
7 | 
 | 
T21 | 
4 | 
| others[2] | 
117 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
2 | 
 | 
T21 | 
2 | 
| others[3] | 
169 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
8 | 
 | 
T21 | 
4 | 
| false | 
40 | 
1 | 
 | 
T21 | 
5 | 
 | 
T75 | 
2 | 
 | 
T352 | 
1 | 
| true | 
6345 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
244 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
10 | 
 | 
T21 | 
5 | 
| others[1] | 
241 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
6 | 
 | 
T19 | 
1 | 
| others[2] | 
219 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
14 | 
 | 
T21 | 
8 | 
| others[3] | 
374 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
19 | 
 | 
T6 | 
1 | 
| false | 
135 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
7 | 
 | 
T21 | 
7 | 
| true | 
5670 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1075 | 
1 | 
 | 
T3 | 
6 | 
 | 
T17 | 
18 | 
 | 
T18 | 
19 | 
| others[1] | 
1061 | 
1 | 
 | 
T3 | 
3 | 
 | 
T16 | 
1 | 
 | 
T17 | 
21 | 
| others[2] | 
1080 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
20 | 
 | 
T18 | 
18 | 
| others[3] | 
1748 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
31 | 
| false | 
535 | 
1 | 
 | 
T17 | 
11 | 
 | 
T6 | 
1 | 
 | 
T18 | 
14 | 
| true | 
1384 | 
1 | 
 | 
T4 | 
1 | 
 | 
T19 | 
1 | 
 | 
T7 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
201 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
10 | 
 | 
T21 | 
5 | 
| others[1] | 
232 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
9 | 
 | 
T21 | 
20 | 
| others[2] | 
213 | 
1 | 
 | 
T17 | 
8 | 
 | 
T6 | 
1 | 
 | 
T18 | 
8 | 
| others[3] | 
397 | 
1 | 
 | 
T17 | 
19 | 
 | 
T18 | 
15 | 
 | 
T21 | 
15 | 
| false | 
133 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
2 | 
 | 
T21 | 
2 | 
| true | 
5707 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
236 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
10 | 
 | 
T21 | 
16 | 
| others[1] | 
225 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
8 | 
 | 
T21 | 
10 | 
| others[2] | 
214 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
7 | 
 | 
T21 | 
11 | 
| others[3] | 
391 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
24 | 
| false | 
105 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
3 | 
 | 
T21 | 
5 | 
| true | 
5712 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1236 | 
1 | 
 | 
T3 | 
5 | 
 | 
T16 | 
1 | 
 | 
T17 | 
12 | 
| others[1] | 
1272 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
19 | 
 | 
T18 | 
21 | 
| others[2] | 
1241 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
30 | 
| others[3] | 
2060 | 
1 | 
 | 
T3 | 
5 | 
 | 
T17 | 
29 | 
 | 
T18 | 
34 | 
| false | 
642 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
9 | 
| true | 
432 | 
1 | 
 | 
T4 | 
1 | 
 | 
T19 | 
1 | 
 | 
T11 | 
2 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1262 | 
1 | 
 | 
T3 | 
5 | 
 | 
T16 | 
1 | 
 | 
T17 | 
14 | 
| others[1] | 
1272 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
25 | 
 | 
T18 | 
19 | 
| others[2] | 
1218 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
24 | 
 | 
T18 | 
12 | 
| others[3] | 
2062 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
28 | 
 | 
T18 | 
39 | 
| false | 
638 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
10 | 
 | 
T18 | 
8 | 
| true | 
431 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
115 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
3 | 
 | 
T21 | 
1 | 
| others[1] | 
106 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
3 | 
 | 
T21 | 
10 | 
| others[2] | 
105 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
8 | 
 | 
T21 | 
1 | 
| others[3] | 
173 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
7 | 
 | 
T21 | 
4 | 
| false | 
58 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
1 | 
 | 
T21 | 
1 | 
| true | 
6326 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
249 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
12 | 
 | 
T7 | 
1 | 
| others[1] | 
254 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
12 | 
 | 
T21 | 
12 | 
| others[2] | 
274 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
13 | 
 | 
T21 | 
16 | 
| others[3] | 
363 | 
1 | 
 | 
T17 | 
17 | 
 | 
T6 | 
1 | 
 | 
T18 | 
16 | 
| false | 
121 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
5 | 
 | 
T19 | 
1 | 
| true | 
5622 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1056 | 
1 | 
 | 
T3 | 
3 | 
 | 
T16 | 
1 | 
 | 
T17 | 
19 | 
| others[1] | 
1117 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
24 | 
 | 
T18 | 
15 | 
| others[2] | 
1059 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
15 | 
| others[3] | 
1708 | 
1 | 
 | 
T3 | 
5 | 
 | 
T17 | 
36 | 
 | 
T18 | 
27 | 
| false | 
558 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
7 | 
 | 
T18 | 
11 | 
| true | 
1385 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 | 
T19 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
235 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
7 | 
 | 
T21 | 
10 | 
| others[1] | 
222 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
10 | 
 | 
T7 | 
1 | 
| others[2] | 
220 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
3 | 
 | 
T21 | 
8 | 
| others[3] | 
397 | 
1 | 
 | 
T17 | 
16 | 
 | 
T6 | 
1 | 
 | 
T18 | 
17 | 
| false | 
114 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
8 | 
 | 
T21 | 
3 | 
| true | 
5695 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
197 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
9 | 
 | 
T21 | 
6 | 
| others[1] | 
222 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
13 | 
 | 
T21 | 
13 | 
| others[2] | 
230 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
10 | 
 | 
T21 | 
11 | 
| others[3] | 
386 | 
1 | 
 | 
T17 | 
18 | 
 | 
T18 | 
13 | 
 | 
T21 | 
18 | 
| false | 
93 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
8 | 
 | 
T21 | 
6 | 
| true | 
5755 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1225 | 
1 | 
 | 
T3 | 
2 | 
 | 
T16 | 
1 | 
 | 
T17 | 
16 | 
| others[1] | 
1276 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
21 | 
 | 
T18 | 
18 | 
| others[2] | 
1224 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
18 | 
 | 
T18 | 
19 | 
| others[3] | 
2057 | 
1 | 
 | 
T3 | 
7 | 
 | 
T17 | 
35 | 
 | 
T18 | 
35 | 
| false | 
649 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
8 | 
 | 
T22 | 
7 | 
| true | 
452 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1253 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
18 | 
 | 
T18 | 
26 | 
| others[1] | 
1269 | 
1 | 
 | 
T3 | 
6 | 
 | 
T17 | 
18 | 
 | 
T18 | 
17 | 
| others[2] | 
1223 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
24 | 
 | 
T18 | 
20 | 
| others[3] | 
2054 | 
1 | 
 | 
T3 | 
3 | 
 | 
T16 | 
1 | 
 | 
T17 | 
33 | 
| false | 
651 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
6 | 
 | 
T22 | 
6 | 
| true | 
433 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T11 | 
2 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
113 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
7 | 
 | 
T21 | 
2 | 
| others[1] | 
120 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
3 | 
 | 
T21 | 
8 | 
| others[2] | 
104 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
5 | 
 | 
T21 | 
2 | 
| others[3] | 
161 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
6 | 
 | 
T21 | 
4 | 
| false | 
49 | 
1 | 
 | 
T17 | 
3 | 
 | 
T21 | 
2 | 
 | 
T40 | 
1 | 
| true | 
6336 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
242 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
7 | 
 | 
T21 | 
5 | 
| others[1] | 
227 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
11 | 
 | 
T19 | 
1 | 
| others[2] | 
212 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
5 | 
 | 
T21 | 
11 | 
| others[3] | 
431 | 
1 | 
 | 
T17 | 
16 | 
 | 
T18 | 
16 | 
 | 
T21 | 
20 | 
| false | 
121 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
9 | 
 | 
T21 | 
4 | 
| true | 
5650 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1080 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
18 | 
 | 
T18 | 
23 | 
| others[1] | 
1018 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
20 | 
 | 
T18 | 
16 | 
| others[2] | 
1040 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
17 | 
| others[3] | 
1823 | 
1 | 
 | 
T3 | 
5 | 
 | 
T17 | 
36 | 
 | 
T18 | 
37 | 
| false | 
581 | 
1 | 
 | 
T16 | 
1 | 
 | 
T17 | 
7 | 
 | 
T18 | 
8 | 
| true | 
1341 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
223 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
13 | 
 | 
T21 | 
6 | 
| others[1] | 
228 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
6 | 
| others[2] | 
217 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
8 | 
 | 
T21 | 
11 | 
| others[3] | 
388 | 
1 | 
 | 
T17 | 
19 | 
 | 
T18 | 
22 | 
 | 
T21 | 
11 | 
| false | 
111 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
8 | 
 | 
T21 | 
9 | 
| true | 
5716 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
235 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
11 | 
| others[1] | 
217 | 
1 | 
 | 
T17 | 
14 | 
 | 
T18 | 
12 | 
 | 
T21 | 
10 | 
| others[2] | 
218 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
9 | 
 | 
T21 | 
11 | 
| others[3] | 
355 | 
1 | 
 | 
T17 | 
16 | 
 | 
T18 | 
11 | 
 | 
T21 | 
14 | 
| false | 
135 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
9 | 
 | 
T21 | 
5 | 
| true | 
5723 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1285 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
24 | 
 | 
T18 | 
18 | 
| others[1] | 
1225 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
3 | 
 | 
T16 | 
1 | 
| others[2] | 
1215 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
15 | 
 | 
T18 | 
19 | 
| others[3] | 
2074 | 
1 | 
 | 
T3 | 
6 | 
 | 
T17 | 
29 | 
 | 
T18 | 
32 | 
| false | 
641 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
12 | 
| true | 
443 | 
1 | 
 | 
T4 | 
1 | 
 | 
T19 | 
1 | 
 | 
T11 | 
2 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1290 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
23 | 
 | 
T18 | 
23 | 
| others[1] | 
1233 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
18 | 
 | 
T18 | 
12 | 
| others[2] | 
1244 | 
1 | 
 | 
T3 | 
2 | 
 | 
T16 | 
1 | 
 | 
T17 | 
18 | 
| others[3] | 
2042 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
29 | 
 | 
T18 | 
38 | 
| false | 
642 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
13 | 
 | 
T18 | 
9 | 
| true | 
432 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
97 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
3 | 
 | 
T21 | 
8 | 
| others[1] | 
104 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
7 | 
 | 
T21 | 
4 | 
| others[2] | 
94 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
7 | 
 | 
T21 | 
2 | 
| others[3] | 
174 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
6 | 
 | 
T21 | 
9 | 
| false | 
48 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
2 | 
 | 
T21 | 
1 | 
| true | 
6366 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
215 | 
1 | 
 | 
T17 | 
12 | 
 | 
T18 | 
13 | 
 | 
T21 | 
9 | 
| others[1] | 
258 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
5 | 
 | 
T21 | 
7 | 
| others[2] | 
217 | 
1 | 
 | 
T17 | 
5 | 
 | 
T6 | 
1 | 
 | 
T18 | 
13 | 
| others[3] | 
406 | 
1 | 
 | 
T17 | 
19 | 
 | 
T18 | 
14 | 
 | 
T21 | 
18 | 
| false | 
117 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
5 | 
 | 
T21 | 
7 | 
| true | 
5670 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1041 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
17 | 
 | 
T18 | 
24 | 
| others[1] | 
1077 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
14 | 
 | 
T7 | 
1 | 
| others[2] | 
1078 | 
1 | 
 | 
T3 | 
1 | 
 | 
T16 | 
1 | 
 | 
T17 | 
18 | 
| others[3] | 
1783 | 
1 | 
 | 
T3 | 
8 | 
 | 
T4 | 
1 | 
 | 
T17 | 
36 | 
| false | 
529 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
10 | 
 | 
T18 | 
9 | 
| true | 
1375 | 
1 | 
 | 
T2 | 
1 | 
 | 
T6 | 
1 | 
 | 
T11 | 
2 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
261 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
11 | 
 | 
T21 | 
11 | 
| others[1] | 
233 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
12 | 
 | 
T21 | 
13 | 
| others[2] | 
225 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
5 | 
 | 
T21 | 
7 | 
| others[3] | 
370 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
13 | 
 | 
T18 | 
14 | 
| false | 
94 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
5 | 
 | 
T21 | 
6 | 
| true | 
5700 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
192 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
7 | 
| others[1] | 
211 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
9 | 
 | 
T21 | 
10 | 
| others[2] | 
214 | 
1 | 
 | 
T17 | 
10 | 
 | 
T18 | 
7 | 
 | 
T21 | 
12 | 
| others[3] | 
358 | 
1 | 
 | 
T17 | 
14 | 
 | 
T18 | 
15 | 
 | 
T21 | 
14 | 
| false | 
115 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
7 | 
 | 
T21 | 
4 | 
| true | 
5793 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1240 | 
1 | 
 | 
T3 | 
2 | 
 | 
T16 | 
1 | 
 | 
T17 | 
14 | 
| others[1] | 
1248 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
16 | 
 | 
T18 | 
22 | 
| others[2] | 
1257 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
20 | 
 | 
T18 | 
14 | 
| others[3] | 
2057 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
41 | 
 | 
T18 | 
29 | 
| false | 
637 | 
1 | 
 | 
T3 | 
3 | 
 | 
T17 | 
10 | 
 | 
T18 | 
13 | 
| true | 
444 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T6 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1250 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
22 | 
 | 
T18 | 
13 | 
| others[1] | 
1263 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
21 | 
 | 
T6 | 
1 | 
| others[2] | 
1231 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
22 | 
 | 
T18 | 
18 | 
| others[3] | 
2099 | 
1 | 
 | 
T3 | 
3 | 
 | 
T16 | 
1 | 
 | 
T17 | 
25 | 
| false | 
610 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
12 | 
| true | 
430 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T19 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
112 | 
1 | 
 | 
T17 | 
4 | 
 | 
T18 | 
1 | 
 | 
T21 | 
7 | 
| others[1] | 
93 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
2 | 
 | 
T75 | 
5 | 
| others[2] | 
100 | 
1 | 
 | 
T17 | 
3 | 
 | 
T18 | 
4 | 
 | 
T21 | 
5 | 
| others[3] | 
176 | 
1 | 
 | 
T17 | 
6 | 
 | 
T18 | 
5 | 
 | 
T21 | 
7 | 
| false | 
55 | 
1 | 
 | 
T17 | 
2 | 
 | 
T18 | 
2 | 
 | 
T21 | 
2 | 
| true | 
6347 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
227 | 
1 | 
 | 
T17 | 
8 | 
 | 
T18 | 
13 | 
 | 
T7 | 
1 | 
| others[1] | 
226 | 
1 | 
 | 
T17 | 
11 | 
 | 
T18 | 
11 | 
 | 
T21 | 
8 | 
| others[2] | 
231 | 
1 | 
 | 
T4 | 
1 | 
 | 
T17 | 
9 | 
 | 
T18 | 
11 | 
| others[3] | 
397 | 
1 | 
 | 
T17 | 
19 | 
 | 
T18 | 
14 | 
 | 
T21 | 
17 | 
| false | 
105 | 
1 | 
 | 
T17 | 
5 | 
 | 
T18 | 
6 | 
 | 
T21 | 
7 | 
| true | 
5697 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
13 | 
 | 
T16 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1063 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
15 | 
 | 
T18 | 
16 | 
| others[1] | 
1049 | 
1 | 
 | 
T3 | 
4 | 
 | 
T16 | 
1 | 
 | 
T17 | 
16 | 
| others[2] | 
1034 | 
1 | 
 | 
T3 | 
2 | 
 | 
T4 | 
1 | 
 | 
T17 | 
18 | 
| others[3] | 
1799 | 
1 | 
 | 
T3 | 
4 | 
 | 
T17 | 
40 | 
 | 
T18 | 
29 | 
| false | 
557 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
2 | 
 | 
T17 | 
12 | 
| true | 
1381 | 
1 | 
 | 
T6 | 
1 | 
 | 
T19 | 
1 | 
 | 
T11 | 
2 | 
 
 
 
| 0% | 
10% | 
20% | 
30% | 
40% | 
50% | 
60% | 
70% | 
80% | 
90% | 
100% |