Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T3 |
2 |
|
T17 |
20 |
|
T18 |
23 |
| others[1] |
1261 |
1 |
|
T3 |
2 |
|
T17 |
17 |
|
T18 |
20 |
| others[2] |
1280 |
1 |
|
T3 |
2 |
|
T17 |
20 |
|
T18 |
20 |
| others[3] |
2028 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T17 |
32 |
| false |
625 |
1 |
|
T3 |
1 |
|
T17 |
12 |
|
T18 |
6 |
| true |
433 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T17 |
2 |
|
T18 |
3 |
|
T21 |
5 |
| others[1] |
109 |
1 |
|
T17 |
8 |
|
T18 |
5 |
|
T21 |
1 |
| others[2] |
89 |
1 |
|
T17 |
3 |
|
T18 |
2 |
|
T21 |
4 |
| others[3] |
174 |
1 |
|
T17 |
10 |
|
T18 |
6 |
|
T21 |
6 |
| false |
52 |
1 |
|
T17 |
4 |
|
T18 |
1 |
|
T21 |
3 |
| true |
6362 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T17 |
10 |
|
T18 |
7 |
|
T21 |
9 |
| others[1] |
251 |
1 |
|
T17 |
9 |
|
T18 |
13 |
|
T21 |
7 |
| others[2] |
207 |
1 |
|
T17 |
11 |
|
T18 |
6 |
|
T7 |
1 |
| others[3] |
391 |
1 |
|
T17 |
13 |
|
T6 |
1 |
|
T18 |
17 |
| false |
121 |
1 |
|
T4 |
1 |
|
T17 |
5 |
|
T18 |
9 |
| true |
5687 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1018 |
1 |
|
T3 |
2 |
|
T17 |
10 |
|
T18 |
23 |
| others[1] |
1073 |
1 |
|
T3 |
3 |
|
T17 |
20 |
|
T18 |
22 |
| others[2] |
1066 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[3] |
1805 |
1 |
|
T3 |
5 |
|
T17 |
38 |
|
T6 |
1 |
| false |
553 |
1 |
|
T3 |
2 |
|
T17 |
6 |
|
T18 |
11 |
| true |
1368 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T17 |
5 |
|
T18 |
8 |
|
T21 |
9 |
| others[1] |
253 |
1 |
|
T17 |
10 |
|
T18 |
9 |
|
T21 |
8 |
| others[2] |
223 |
1 |
|
T17 |
10 |
|
T18 |
8 |
|
T21 |
12 |
| others[3] |
408 |
1 |
|
T17 |
12 |
|
T18 |
17 |
|
T7 |
1 |
| false |
119 |
1 |
|
T4 |
1 |
|
T17 |
5 |
|
T6 |
1 |
| true |
5660 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T17 |
10 |
|
T18 |
10 |
|
T21 |
6 |
| others[1] |
213 |
1 |
|
T17 |
9 |
|
T18 |
18 |
|
T21 |
7 |
| others[2] |
225 |
1 |
|
T17 |
10 |
|
T18 |
11 |
|
T21 |
11 |
| others[3] |
367 |
1 |
|
T4 |
1 |
|
T17 |
18 |
|
T18 |
12 |
| false |
120 |
1 |
|
T17 |
7 |
|
T18 |
6 |
|
T21 |
6 |
| true |
5739 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T3 |
1 |
|
T17 |
13 |
|
T18 |
24 |
| others[1] |
1283 |
1 |
|
T3 |
6 |
|
T17 |
26 |
|
T18 |
17 |
| others[2] |
1201 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
18 |
| others[3] |
2091 |
1 |
|
T3 |
3 |
|
T17 |
36 |
|
T18 |
32 |
| false |
657 |
1 |
|
T3 |
1 |
|
T17 |
8 |
|
T18 |
14 |
| true |
438 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T3 |
2 |
|
T17 |
15 |
|
T18 |
28 |
| others[1] |
1196 |
1 |
|
T3 |
2 |
|
T17 |
25 |
|
T18 |
15 |
| others[2] |
1244 |
1 |
|
T3 |
3 |
|
T17 |
14 |
|
T18 |
21 |
| others[3] |
2044 |
1 |
|
T3 |
4 |
|
T16 |
1 |
|
T17 |
35 |
| false |
721 |
1 |
|
T3 |
2 |
|
T17 |
12 |
|
T18 |
5 |
| true |
429 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
86 |
1 |
|
T17 |
6 |
|
T18 |
4 |
|
T21 |
1 |
| others[1] |
116 |
1 |
|
T17 |
1 |
|
T18 |
6 |
|
T21 |
6 |
| others[2] |
105 |
1 |
|
T17 |
6 |
|
T18 |
4 |
|
T21 |
4 |
| others[3] |
185 |
1 |
|
T17 |
8 |
|
T18 |
6 |
|
T21 |
9 |
| false |
65 |
1 |
|
T17 |
1 |
|
T18 |
2 |
|
T21 |
2 |
| true |
6326 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T4 |
1 |
|
T17 |
13 |
|
T18 |
7 |
| others[1] |
205 |
1 |
|
T17 |
9 |
|
T18 |
8 |
|
T7 |
1 |
| others[2] |
222 |
1 |
|
T17 |
13 |
|
T18 |
7 |
|
T21 |
8 |
| others[3] |
383 |
1 |
|
T17 |
10 |
|
T18 |
22 |
|
T19 |
1 |
| false |
136 |
1 |
|
T17 |
6 |
|
T18 |
7 |
|
T21 |
6 |
| true |
5714 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1032 |
1 |
|
T3 |
3 |
|
T17 |
20 |
|
T18 |
19 |
| others[1] |
1066 |
1 |
|
T3 |
2 |
|
T17 |
12 |
|
T6 |
1 |
| others[2] |
1072 |
1 |
|
T3 |
3 |
|
T17 |
16 |
|
T18 |
24 |
| others[3] |
1780 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
38 |
| false |
562 |
1 |
|
T3 |
3 |
|
T17 |
15 |
|
T18 |
11 |
| true |
1371 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T17 |
16 |
|
T18 |
14 |
|
T21 |
9 |
| others[1] |
233 |
1 |
|
T17 |
7 |
|
T6 |
1 |
|
T18 |
16 |
| others[2] |
233 |
1 |
|
T17 |
13 |
|
T18 |
9 |
|
T21 |
9 |
| others[3] |
393 |
1 |
|
T17 |
17 |
|
T18 |
14 |
|
T7 |
1 |
| false |
139 |
1 |
|
T17 |
6 |
|
T18 |
7 |
|
T21 |
9 |
| true |
5639 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T17 |
8 |
|
T18 |
11 |
|
T21 |
11 |
| others[1] |
206 |
1 |
|
T17 |
6 |
|
T18 |
8 |
|
T21 |
4 |
| others[2] |
217 |
1 |
|
T17 |
9 |
|
T18 |
3 |
|
T21 |
15 |
| others[3] |
380 |
1 |
|
T17 |
18 |
|
T18 |
17 |
|
T21 |
15 |
| false |
117 |
1 |
|
T17 |
4 |
|
T18 |
5 |
|
T21 |
4 |
| true |
5730 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
17 |
| others[1] |
1235 |
1 |
|
T3 |
5 |
|
T17 |
24 |
|
T18 |
25 |
| others[2] |
1284 |
1 |
|
T3 |
1 |
|
T17 |
15 |
|
T6 |
1 |
| others[3] |
1994 |
1 |
|
T3 |
4 |
|
T17 |
35 |
|
T18 |
28 |
| false |
649 |
1 |
|
T3 |
2 |
|
T17 |
10 |
|
T18 |
11 |
| true |
455 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1181 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
18 |
| others[1] |
1275 |
1 |
|
T3 |
5 |
|
T17 |
26 |
|
T18 |
15 |
| others[2] |
1237 |
1 |
|
T3 |
2 |
|
T17 |
17 |
|
T18 |
20 |
| others[3] |
2106 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T17 |
31 |
| false |
659 |
1 |
|
T3 |
1 |
|
T17 |
9 |
|
T18 |
9 |
| true |
425 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T17 |
3 |
|
T18 |
1 |
|
T21 |
3 |
| others[1] |
106 |
1 |
|
T17 |
3 |
|
T18 |
1 |
|
T21 |
5 |
| others[2] |
116 |
1 |
|
T17 |
7 |
|
T18 |
4 |
|
T21 |
2 |
| others[3] |
165 |
1 |
|
T17 |
6 |
|
T18 |
11 |
|
T21 |
5 |
| false |
53 |
1 |
|
T17 |
2 |
|
T18 |
2 |
|
T21 |
3 |
| true |
6350 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T17 |
10 |
|
T18 |
17 |
|
T7 |
1 |
| others[1] |
232 |
1 |
|
T4 |
1 |
|
T17 |
7 |
|
T18 |
14 |
| others[2] |
241 |
1 |
|
T17 |
9 |
|
T6 |
1 |
|
T18 |
7 |
| others[3] |
386 |
1 |
|
T17 |
10 |
|
T18 |
17 |
|
T19 |
1 |
| false |
120 |
1 |
|
T17 |
7 |
|
T18 |
4 |
|
T21 |
4 |
| true |
5672 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T3 |
3 |
|
T17 |
21 |
|
T18 |
21 |
| others[1] |
1038 |
1 |
|
T16 |
1 |
|
T17 |
20 |
|
T18 |
14 |
| others[2] |
1067 |
1 |
|
T3 |
3 |
|
T17 |
24 |
|
T18 |
17 |
| others[3] |
1818 |
1 |
|
T3 |
4 |
|
T17 |
31 |
|
T18 |
35 |
| false |
528 |
1 |
|
T3 |
3 |
|
T17 |
5 |
|
T6 |
1 |
| true |
1359 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T17 |
7 |
|
T18 |
9 |
|
T19 |
1 |
| others[1] |
252 |
1 |
|
T17 |
12 |
|
T18 |
10 |
|
T21 |
20 |
| others[2] |
227 |
1 |
|
T17 |
16 |
|
T18 |
10 |
|
T7 |
1 |
| others[3] |
365 |
1 |
|
T4 |
1 |
|
T17 |
14 |
|
T6 |
1 |
| false |
122 |
1 |
|
T17 |
6 |
|
T18 |
2 |
|
T21 |
9 |
| true |
5691 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
187 |
1 |
|
T17 |
8 |
|
T18 |
8 |
|
T21 |
10 |
| others[1] |
217 |
1 |
|
T17 |
10 |
|
T18 |
5 |
|
T21 |
11 |
| others[2] |
252 |
1 |
|
T4 |
1 |
|
T17 |
11 |
|
T18 |
12 |
| others[3] |
366 |
1 |
|
T17 |
17 |
|
T18 |
23 |
|
T21 |
10 |
| false |
101 |
1 |
|
T17 |
6 |
|
T18 |
5 |
|
T21 |
2 |
| true |
5760 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
19 |
| others[1] |
1241 |
1 |
|
T3 |
2 |
|
T17 |
19 |
|
T18 |
22 |
| others[2] |
1243 |
1 |
|
T3 |
4 |
|
T17 |
21 |
|
T18 |
20 |
| others[3] |
2087 |
1 |
|
T3 |
5 |
|
T4 |
1 |
|
T17 |
31 |
| false |
617 |
1 |
|
T3 |
1 |
|
T17 |
11 |
|
T18 |
10 |
| true |
447 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T3 |
2 |
|
T17 |
21 |
|
T18 |
16 |
| others[1] |
1217 |
1 |
|
T3 |
3 |
|
T17 |
22 |
|
T18 |
18 |
| others[2] |
1201 |
1 |
|
T3 |
4 |
|
T17 |
21 |
|
T18 |
22 |
| others[3] |
2135 |
1 |
|
T3 |
3 |
|
T16 |
1 |
|
T17 |
27 |
| false |
619 |
1 |
|
T3 |
1 |
|
T17 |
10 |
|
T18 |
6 |
| true |
437 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T17 |
4 |
|
T18 |
4 |
|
T21 |
5 |
| others[1] |
114 |
1 |
|
T4 |
1 |
|
T17 |
3 |
|
T18 |
5 |
| others[2] |
112 |
1 |
|
T17 |
6 |
|
T18 |
1 |
|
T21 |
5 |
| others[3] |
165 |
1 |
|
T17 |
3 |
|
T18 |
8 |
|
T21 |
6 |
| false |
53 |
1 |
|
T17 |
1 |
|
T18 |
3 |
|
T351 |
1 |
| true |
6333 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T17 |
6 |
|
T18 |
10 |
|
T21 |
10 |
| others[1] |
242 |
1 |
|
T4 |
1 |
|
T17 |
11 |
|
T6 |
1 |
| others[2] |
234 |
1 |
|
T17 |
10 |
|
T18 |
9 |
|
T21 |
7 |
| others[3] |
356 |
1 |
|
T17 |
11 |
|
T18 |
18 |
|
T7 |
1 |
| false |
113 |
1 |
|
T17 |
7 |
|
T18 |
6 |
|
T21 |
3 |
| true |
5697 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1077 |
1 |
|
T3 |
4 |
|
T17 |
18 |
|
T18 |
23 |
| others[1] |
1063 |
1 |
|
T3 |
2 |
|
T17 |
15 |
|
T18 |
21 |
| others[2] |
1010 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
16 |
| others[3] |
1816 |
1 |
|
T3 |
3 |
|
T4 |
1 |
|
T16 |
1 |
| false |
523 |
1 |
|
T3 |
3 |
|
T17 |
11 |
|
T18 |
14 |
| true |
1394 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T17 |
12 |
|
T18 |
12 |
|
T21 |
9 |
| others[1] |
227 |
1 |
|
T17 |
11 |
|
T18 |
5 |
|
T19 |
1 |
| others[2] |
239 |
1 |
|
T17 |
11 |
|
T18 |
11 |
|
T21 |
8 |
| others[3] |
396 |
1 |
|
T17 |
23 |
|
T18 |
12 |
|
T21 |
21 |
| false |
121 |
1 |
|
T17 |
3 |
|
T6 |
1 |
|
T18 |
4 |
| true |
5669 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T17 |
9 |
|
T18 |
8 |
|
T21 |
8 |
| others[1] |
220 |
1 |
|
T17 |
7 |
|
T18 |
9 |
|
T21 |
10 |
| others[2] |
237 |
1 |
|
T17 |
5 |
|
T18 |
12 |
|
T21 |
8 |
| others[3] |
336 |
1 |
|
T4 |
1 |
|
T17 |
15 |
|
T18 |
13 |
| false |
115 |
1 |
|
T17 |
2 |
|
T18 |
2 |
|
T21 |
4 |
| true |
5772 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T3 |
3 |
|
T16 |
1 |
|
T17 |
21 |
| others[1] |
1233 |
1 |
|
T3 |
5 |
|
T17 |
23 |
|
T18 |
27 |
| others[2] |
1248 |
1 |
|
T3 |
3 |
|
T17 |
21 |
|
T18 |
19 |
| others[3] |
2063 |
1 |
|
T3 |
1 |
|
T17 |
27 |
|
T18 |
33 |
| false |
631 |
1 |
|
T3 |
1 |
|
T17 |
9 |
|
T18 |
8 |
| true |
448 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T159 |
1 |
|
T353 |
1 |
|
T354 |
1 |
| others[1] |
6 |
1 |
|
T92 |
1 |
|
T355 |
1 |
|
T356 |
1 |
| others[2] |
8 |
1 |
|
T156 |
1 |
|
T141 |
1 |
|
T357 |
1 |
| others[3] |
16 |
1 |
|
T145 |
1 |
|
T219 |
1 |
|
T155 |
1 |
| false |
3 |
1 |
|
T358 |
1 |
|
T359 |
1 |
|
T360 |
1 |
| true |
37 |
1 |
|
T12 |
1 |
|
T70 |
1 |
|
T130 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T361 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
2 |
1 |
|
T362 |
1 |
|
T363 |
1 |
|
- |
- |
| others[2] |
1 |
1 |
|
T364 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
4 |
1 |
|
T365 |
1 |
|
T366 |
1 |
|
T367 |
1 |
| false |
13 |
1 |
|
T30 |
1 |
|
T343 |
1 |
|
T235 |
1 |
| true |
24 |
1 |
|
T1 |
1 |
|
T166 |
1 |
|
T368 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T362 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
6 |
1 |
|
T369 |
1 |
|
T370 |
1 |
|
T371 |
1 |
| others[2] |
2 |
1 |
|
T361 |
1 |
|
T372 |
1 |
|
- |
- |
| others[3] |
7 |
1 |
|
T373 |
1 |
|
T374 |
1 |
|
T375 |
1 |
| false |
10 |
1 |
|
T166 |
1 |
|
T368 |
1 |
|
T376 |
1 |
| true |
19 |
1 |
|
T1 |
1 |
|
T30 |
1 |
|
T343 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |