Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10109 |
1 |
|
T3 |
2 |
|
T5 |
1 |
|
T17 |
16 |
| others[1] |
805 |
1 |
|
T3 |
3 |
|
T16 |
1 |
|
T17 |
22 |
| others[2] |
765 |
1 |
|
T3 |
5 |
|
T17 |
20 |
|
T18 |
13 |
| others[3] |
1341 |
1 |
|
T3 |
3 |
|
T4 |
1 |
|
T17 |
31 |
| false |
414 |
1 |
|
T17 |
12 |
|
T18 |
13 |
|
T22 |
2 |
| true |
515 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2326 |
1 |
|
T3 |
5 |
|
T17 |
6 |
|
T18 |
5 |
| others[1] |
2380 |
1 |
|
T3 |
4 |
|
T17 |
7 |
|
T18 |
11 |
| others[2] |
2384 |
1 |
|
T3 |
2 |
|
T17 |
9 |
|
T18 |
12 |
| others[3] |
4027 |
1 |
|
T3 |
2 |
|
T17 |
19 |
|
T18 |
12 |
| false |
1249 |
1 |
|
T16 |
1 |
|
T17 |
5 |
|
T18 |
2 |
| true |
1583 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9556 |
1 |
|
T17 |
18 |
|
T18 |
10 |
|
T46 |
125 |
| others[1] |
298 |
1 |
|
T17 |
4 |
|
T18 |
13 |
|
T7 |
1 |
| others[2] |
255 |
1 |
|
T17 |
6 |
|
T18 |
11 |
|
T19 |
1 |
| others[3] |
462 |
1 |
|
T17 |
9 |
|
T18 |
18 |
|
T21 |
17 |
| false |
131 |
1 |
|
T17 |
5 |
|
T18 |
3 |
|
T21 |
4 |
| true |
3247 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9783 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T5 |
1 |
| others[1] |
462 |
1 |
|
T4 |
1 |
|
T17 |
8 |
|
T18 |
12 |
| others[2] |
499 |
1 |
|
T3 |
1 |
|
T17 |
13 |
|
T18 |
12 |
| others[3] |
795 |
1 |
|
T17 |
23 |
|
T6 |
1 |
|
T18 |
16 |
| false |
246 |
1 |
|
T17 |
7 |
|
T18 |
1 |
|
T7 |
1 |
| true |
2164 |
1 |
|
T2 |
1 |
|
T3 |
11 |
|
T17 |
40 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9581 |
1 |
|
T17 |
11 |
|
T18 |
12 |
|
T46 |
125 |
| others[1] |
270 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T17 |
11 |
| others[2] |
252 |
1 |
|
T17 |
9 |
|
T18 |
10 |
|
T39 |
1 |
| others[3] |
452 |
1 |
|
T17 |
16 |
|
T6 |
1 |
|
T18 |
21 |
| false |
142 |
1 |
|
T17 |
4 |
|
T18 |
6 |
|
T21 |
4 |
| true |
3252 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9552 |
1 |
|
T17 |
18 |
|
T18 |
12 |
|
T46 |
125 |
| others[1] |
239 |
1 |
|
T17 |
18 |
|
T18 |
7 |
|
T21 |
8 |
| others[2] |
255 |
1 |
|
T17 |
7 |
|
T18 |
7 |
|
T21 |
11 |
| others[3] |
465 |
1 |
|
T16 |
1 |
|
T17 |
20 |
|
T18 |
19 |
| false |
118 |
1 |
|
T17 |
3 |
|
T18 |
4 |
|
T21 |
3 |
| true |
3320 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10174 |
1 |
|
T3 |
5 |
|
T16 |
1 |
|
T5 |
1 |
| others[1] |
789 |
1 |
|
T3 |
1 |
|
T17 |
19 |
|
T18 |
20 |
| others[2] |
750 |
1 |
|
T3 |
3 |
|
T17 |
23 |
|
T18 |
14 |
| others[3] |
1307 |
1 |
|
T3 |
3 |
|
T17 |
29 |
|
T18 |
34 |
| false |
433 |
1 |
|
T3 |
1 |
|
T17 |
13 |
|
T18 |
9 |
| true |
496 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10104 |
1 |
|
T3 |
1 |
|
T17 |
19 |
|
T18 |
23 |
| others[1] |
803 |
1 |
|
T3 |
2 |
|
T17 |
20 |
|
T18 |
15 |
| others[2] |
791 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T17 |
27 |
| others[3] |
1291 |
1 |
|
T3 |
3 |
|
T17 |
28 |
|
T18 |
34 |
| false |
410 |
1 |
|
T3 |
1 |
|
T17 |
7 |
|
T18 |
9 |
| true |
518 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2377 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T17 |
11 |
| others[1] |
2361 |
1 |
|
T3 |
2 |
|
T17 |
7 |
|
T18 |
10 |
| others[2] |
2372 |
1 |
|
T3 |
4 |
|
T16 |
1 |
|
T17 |
6 |
| others[3] |
3910 |
1 |
|
T3 |
4 |
|
T17 |
15 |
|
T18 |
21 |
| false |
1312 |
1 |
|
T3 |
1 |
|
T17 |
7 |
|
T18 |
3 |
| true |
1585 |
1 |
|
T2 |
1 |
|
T17 |
55 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9569 |
1 |
|
T17 |
11 |
|
T18 |
13 |
|
T7 |
1 |
| others[1] |
252 |
1 |
|
T17 |
10 |
|
T18 |
9 |
|
T34 |
1 |
| others[2] |
296 |
1 |
|
T17 |
8 |
|
T18 |
12 |
|
T21 |
10 |
| others[3] |
395 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T17 |
18 |
| false |
117 |
1 |
|
T17 |
3 |
|
T18 |
4 |
|
T21 |
4 |
| true |
3288 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T17 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9757 |
1 |
|
T3 |
1 |
|
T17 |
9 |
|
T18 |
12 |
| others[1] |
482 |
1 |
|
T3 |
1 |
|
T17 |
9 |
|
T6 |
1 |
| others[2] |
449 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T17 |
8 |
| others[3] |
806 |
1 |
|
T17 |
15 |
|
T18 |
18 |
|
T22 |
3 |
| false |
240 |
1 |
|
T3 |
1 |
|
T17 |
6 |
|
T18 |
4 |
| true |
2183 |
1 |
|
T3 |
8 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9549 |
1 |
|
T16 |
1 |
|
T17 |
10 |
|
T18 |
5 |
| others[1] |
258 |
1 |
|
T17 |
8 |
|
T18 |
9 |
|
T19 |
1 |
| others[2] |
281 |
1 |
|
T17 |
12 |
|
T18 |
13 |
|
T21 |
10 |
| others[3] |
472 |
1 |
|
T17 |
15 |
|
T18 |
23 |
|
T34 |
1 |
| false |
136 |
1 |
|
T17 |
4 |
|
T18 |
5 |
|
T21 |
2 |
| true |
3221 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9546 |
1 |
|
T17 |
13 |
|
T18 |
12 |
|
T46 |
125 |
| others[1] |
245 |
1 |
|
T17 |
10 |
|
T18 |
12 |
|
T21 |
4 |
| others[2] |
244 |
1 |
|
T16 |
1 |
|
T17 |
6 |
|
T18 |
8 |
| others[3] |
402 |
1 |
|
T17 |
13 |
|
T18 |
12 |
|
T34 |
1 |
| false |
134 |
1 |
|
T4 |
1 |
|
T17 |
8 |
|
T18 |
7 |
| true |
3346 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T17 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10088 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
| others[1] |
844 |
1 |
|
T3 |
4 |
|
T17 |
28 |
|
T18 |
19 |
| others[2] |
776 |
1 |
|
T3 |
3 |
|
T17 |
13 |
|
T18 |
16 |
| others[3] |
1314 |
1 |
|
T3 |
5 |
|
T17 |
33 |
|
T18 |
25 |
| false |
400 |
1 |
|
T17 |
14 |
|
T18 |
14 |
|
T22 |
7 |
| true |
495 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10041 |
1 |
|
T3 |
2 |
|
T17 |
25 |
|
T6 |
1 |
| others[1] |
820 |
1 |
|
T3 |
2 |
|
T17 |
19 |
|
T18 |
22 |
| others[2] |
812 |
1 |
|
T3 |
2 |
|
T17 |
20 |
|
T18 |
24 |
| others[3] |
1314 |
1 |
|
T3 |
7 |
|
T16 |
1 |
|
T17 |
31 |
| false |
407 |
1 |
|
T17 |
6 |
|
T18 |
6 |
|
T22 |
3 |
| true |
523 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2402 |
1 |
|
T3 |
2 |
|
T17 |
10 |
|
T18 |
9 |
| others[1] |
2360 |
1 |
|
T3 |
2 |
|
T17 |
10 |
|
T18 |
11 |
| others[2] |
2415 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
9 |
| others[3] |
3955 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T17 |
26 |
| false |
1252 |
1 |
|
T3 |
3 |
|
T17 |
4 |
|
T18 |
6 |
| true |
1533 |
1 |
|
T2 |
1 |
|
T17 |
42 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9572 |
1 |
|
T17 |
13 |
|
T18 |
12 |
|
T46 |
125 |
| others[1] |
265 |
1 |
|
T17 |
9 |
|
T6 |
1 |
|
T18 |
11 |
| others[2] |
294 |
1 |
|
T16 |
1 |
|
T17 |
13 |
|
T18 |
9 |
| others[3] |
446 |
1 |
|
T4 |
1 |
|
T17 |
15 |
|
T18 |
17 |
| false |
135 |
1 |
|
T17 |
1 |
|
T18 |
3 |
|
T39 |
1 |
| true |
3205 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T17 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9757 |
1 |
|
T17 |
9 |
|
T18 |
7 |
|
T19 |
1 |
| others[1] |
442 |
1 |
|
T3 |
1 |
|
T17 |
7 |
|
T18 |
8 |
| others[2] |
435 |
1 |
|
T4 |
1 |
|
T17 |
14 |
|
T18 |
15 |
| others[3] |
791 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
16 |
| false |
247 |
1 |
|
T3 |
3 |
|
T17 |
7 |
|
T18 |
4 |
| true |
2245 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T17 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9583 |
1 |
|
T17 |
15 |
|
T18 |
13 |
|
T46 |
125 |
| others[1] |
280 |
1 |
|
T17 |
12 |
|
T18 |
14 |
|
T19 |
1 |
| others[2] |
254 |
1 |
|
T17 |
8 |
|
T18 |
10 |
|
T7 |
1 |
| others[3] |
415 |
1 |
|
T4 |
1 |
|
T17 |
11 |
|
T18 |
15 |
| false |
117 |
1 |
|
T17 |
7 |
|
T18 |
3 |
|
T21 |
5 |
| true |
3268 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9533 |
1 |
|
T17 |
18 |
|
T18 |
10 |
|
T46 |
125 |
| others[1] |
258 |
1 |
|
T16 |
1 |
|
T17 |
10 |
|
T18 |
6 |
| others[2] |
245 |
1 |
|
T17 |
7 |
|
T18 |
12 |
|
T21 |
12 |
| others[3] |
404 |
1 |
|
T17 |
13 |
|
T18 |
14 |
|
T21 |
12 |
| false |
123 |
1 |
|
T17 |
10 |
|
T18 |
4 |
|
T21 |
6 |
| true |
3354 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10109 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T17 |
14 |
| others[1] |
779 |
1 |
|
T3 |
5 |
|
T17 |
22 |
|
T18 |
21 |
| others[2] |
789 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
20 |
| others[3] |
1337 |
1 |
|
T3 |
4 |
|
T17 |
34 |
|
T18 |
30 |
| false |
387 |
1 |
|
T3 |
1 |
|
T17 |
11 |
|
T18 |
12 |
| true |
516 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10105 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T16 |
1 |
| others[1] |
815 |
1 |
|
T3 |
4 |
|
T17 |
16 |
|
T18 |
31 |
| others[2] |
810 |
1 |
|
T3 |
2 |
|
T17 |
21 |
|
T18 |
14 |
| others[3] |
1283 |
1 |
|
T3 |
2 |
|
T17 |
34 |
|
T18 |
35 |
| false |
394 |
1 |
|
T3 |
1 |
|
T17 |
12 |
|
T18 |
8 |
| true |
510 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2325 |
1 |
|
T3 |
1 |
|
T17 |
6 |
|
T18 |
11 |
| others[1] |
2418 |
1 |
|
T3 |
3 |
|
T17 |
7 |
|
T18 |
10 |
| others[2] |
2351 |
1 |
|
T3 |
3 |
|
T17 |
8 |
|
T18 |
11 |
| others[3] |
3978 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T17 |
15 |
| false |
1260 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
7 |
| true |
1585 |
1 |
|
T2 |
1 |
|
T17 |
58 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9585 |
1 |
|
T17 |
7 |
|
T18 |
9 |
|
T46 |
125 |
| others[1] |
267 |
1 |
|
T17 |
6 |
|
T18 |
11 |
|
T34 |
1 |
| others[2] |
256 |
1 |
|
T17 |
10 |
|
T18 |
12 |
|
T21 |
7 |
| others[3] |
433 |
1 |
|
T4 |
1 |
|
T17 |
18 |
|
T18 |
16 |
| false |
147 |
1 |
|
T17 |
4 |
|
T18 |
3 |
|
T21 |
8 |
| true |
3229 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9688 |
1 |
|
T3 |
1 |
|
T17 |
8 |
|
T18 |
11 |
| others[1] |
449 |
1 |
|
T17 |
9 |
|
T18 |
13 |
|
T22 |
2 |
| others[2] |
488 |
1 |
|
T3 |
1 |
|
T17 |
6 |
|
T18 |
9 |
| others[3] |
762 |
1 |
|
T3 |
1 |
|
T17 |
18 |
|
T6 |
1 |
| false |
250 |
1 |
|
T3 |
1 |
|
T17 |
3 |
|
T18 |
4 |
| true |
2280 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9543 |
1 |
|
T17 |
5 |
|
T18 |
6 |
|
T46 |
125 |
| others[1] |
268 |
1 |
|
T4 |
1 |
|
T17 |
8 |
|
T18 |
5 |
| others[2] |
257 |
1 |
|
T17 |
10 |
|
T18 |
8 |
|
T19 |
1 |
| others[3] |
415 |
1 |
|
T17 |
14 |
|
T18 |
30 |
|
T21 |
15 |
| false |
139 |
1 |
|
T17 |
3 |
|
T18 |
5 |
|
T21 |
7 |
| true |
3295 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9532 |
1 |
|
T17 |
8 |
|
T18 |
12 |
|
T46 |
125 |
| others[1] |
271 |
1 |
|
T17 |
9 |
|
T18 |
10 |
|
T34 |
1 |
| others[2] |
278 |
1 |
|
T17 |
8 |
|
T18 |
17 |
|
T21 |
8 |
| others[3] |
419 |
1 |
|
T17 |
16 |
|
T18 |
11 |
|
T39 |
1 |
| false |
150 |
1 |
|
T17 |
6 |
|
T18 |
8 |
|
T21 |
8 |
| true |
3267 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10085 |
1 |
|
T3 |
2 |
|
T17 |
20 |
|
T18 |
23 |
| others[1] |
805 |
1 |
|
T3 |
4 |
|
T16 |
1 |
|
T17 |
13 |
| others[2] |
752 |
1 |
|
T3 |
2 |
|
T17 |
30 |
|
T18 |
11 |
| others[3] |
1343 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
1 |
| false |
440 |
1 |
|
T17 |
8 |
|
T18 |
9 |
|
T12 |
1 |
| true |
492 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10120 |
1 |
|
T3 |
1 |
|
T17 |
21 |
|
T18 |
17 |
| others[1] |
870 |
1 |
|
T3 |
4 |
|
T17 |
20 |
|
T6 |
1 |
| others[2] |
778 |
1 |
|
T3 |
3 |
|
T17 |
21 |
|
T18 |
18 |
| others[3] |
1259 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T16 |
1 |
| false |
370 |
1 |
|
T3 |
3 |
|
T17 |
6 |
|
T18 |
10 |
| true |
520 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2358 |
1 |
|
T3 |
3 |
|
T17 |
7 |
|
T18 |
16 |
| others[1] |
2370 |
1 |
|
T3 |
1 |
|
T17 |
4 |
|
T18 |
9 |
| others[2] |
2432 |
1 |
|
T3 |
6 |
|
T17 |
15 |
|
T18 |
9 |
| others[3] |
3941 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
22 |
| false |
1258 |
1 |
|
T3 |
1 |
|
T17 |
6 |
|
T18 |
5 |
| true |
1558 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9585 |
1 |
|
T16 |
1 |
|
T17 |
14 |
|
T18 |
16 |
| others[1] |
257 |
1 |
|
T17 |
6 |
|
T6 |
1 |
|
T18 |
9 |
| others[2] |
275 |
1 |
|
T17 |
13 |
|
T18 |
11 |
|
T21 |
7 |
| others[3] |
470 |
1 |
|
T17 |
11 |
|
T18 |
14 |
|
T21 |
15 |
| false |
118 |
1 |
|
T17 |
5 |
|
T18 |
1 |
|
T19 |
1 |
| true |
3212 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |