Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9747 |
1 |
|
T3 |
1 |
|
T17 |
13 |
|
T18 |
11 |
| others[1] |
446 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T16 |
1 |
| others[2] |
477 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
10 |
| others[3] |
758 |
1 |
|
T3 |
1 |
|
T17 |
16 |
|
T18 |
14 |
| false |
222 |
1 |
|
T3 |
1 |
|
T17 |
3 |
|
T18 |
4 |
| true |
2267 |
1 |
|
T3 |
7 |
|
T17 |
51 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9561 |
1 |
|
T17 |
14 |
|
T18 |
8 |
|
T46 |
125 |
| others[1] |
285 |
1 |
|
T17 |
7 |
|
T18 |
8 |
|
T21 |
6 |
| others[2] |
250 |
1 |
|
T17 |
6 |
|
T18 |
14 |
|
T7 |
1 |
| others[3] |
437 |
1 |
|
T16 |
1 |
|
T17 |
22 |
|
T6 |
1 |
| false |
137 |
1 |
|
T17 |
4 |
|
T18 |
8 |
|
T21 |
6 |
| true |
3247 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9539 |
1 |
|
T4 |
1 |
|
T17 |
10 |
|
T18 |
11 |
| others[1] |
252 |
1 |
|
T17 |
8 |
|
T18 |
13 |
|
T21 |
10 |
| others[2] |
259 |
1 |
|
T16 |
1 |
|
T17 |
7 |
|
T18 |
9 |
| others[3] |
404 |
1 |
|
T17 |
18 |
|
T18 |
14 |
|
T39 |
1 |
| false |
141 |
1 |
|
T17 |
6 |
|
T18 |
8 |
|
T21 |
8 |
| true |
3322 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T17 |
52 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10060 |
1 |
|
T3 |
1 |
|
T17 |
18 |
|
T18 |
21 |
| others[1] |
820 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
| others[2] |
788 |
1 |
|
T3 |
3 |
|
T17 |
21 |
|
T18 |
23 |
| others[3] |
1361 |
1 |
|
T3 |
6 |
|
T17 |
23 |
|
T18 |
33 |
| false |
405 |
1 |
|
T3 |
2 |
|
T17 |
16 |
|
T18 |
12 |
| true |
483 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10090 |
1 |
|
T16 |
1 |
|
T17 |
22 |
|
T6 |
1 |
| others[1] |
745 |
1 |
|
T3 |
2 |
|
T17 |
21 |
|
T18 |
16 |
| others[2] |
798 |
1 |
|
T3 |
4 |
|
T17 |
15 |
|
T18 |
27 |
| others[3] |
1339 |
1 |
|
T3 |
4 |
|
T17 |
33 |
|
T18 |
22 |
| false |
438 |
1 |
|
T3 |
3 |
|
T17 |
10 |
|
T18 |
13 |
| true |
507 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2341 |
1 |
|
T3 |
3 |
|
T16 |
1 |
|
T17 |
12 |
| others[1] |
2378 |
1 |
|
T3 |
4 |
|
T17 |
13 |
|
T18 |
6 |
| others[2] |
2348 |
1 |
|
T3 |
2 |
|
T17 |
7 |
|
T18 |
7 |
| others[3] |
4057 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T17 |
21 |
| false |
1251 |
1 |
|
T3 |
2 |
|
T17 |
1 |
|
T18 |
7 |
| true |
1542 |
1 |
|
T2 |
1 |
|
T17 |
47 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9567 |
1 |
|
T17 |
6 |
|
T18 |
9 |
|
T46 |
125 |
| others[1] |
244 |
1 |
|
T17 |
7 |
|
T18 |
5 |
|
T21 |
12 |
| others[2] |
264 |
1 |
|
T17 |
7 |
|
T6 |
1 |
|
T18 |
12 |
| others[3] |
463 |
1 |
|
T17 |
16 |
|
T18 |
15 |
|
T34 |
1 |
| false |
129 |
1 |
|
T17 |
3 |
|
T18 |
4 |
|
T21 |
5 |
| true |
3250 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9776 |
1 |
|
T3 |
1 |
|
T17 |
5 |
|
T18 |
17 |
| others[1] |
453 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
12 |
| others[2] |
477 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
9 |
| others[3] |
768 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T17 |
15 |
| false |
208 |
1 |
|
T17 |
3 |
|
T6 |
1 |
|
T18 |
6 |
| true |
2235 |
1 |
|
T3 |
5 |
|
T17 |
57 |
|
T18 |
43 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9528 |
1 |
|
T17 |
12 |
|
T6 |
1 |
|
T18 |
9 |
| others[1] |
276 |
1 |
|
T17 |
10 |
|
T18 |
10 |
|
T34 |
1 |
| others[2] |
282 |
1 |
|
T17 |
7 |
|
T18 |
12 |
|
T7 |
1 |
| others[3] |
411 |
1 |
|
T17 |
11 |
|
T18 |
18 |
|
T19 |
1 |
| false |
140 |
1 |
|
T17 |
8 |
|
T18 |
8 |
|
T21 |
7 |
| true |
3280 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9540 |
1 |
|
T4 |
1 |
|
T17 |
12 |
|
T18 |
9 |
| others[1] |
243 |
1 |
|
T17 |
7 |
|
T18 |
10 |
|
T21 |
5 |
| others[2] |
251 |
1 |
|
T17 |
12 |
|
T18 |
6 |
|
T21 |
10 |
| others[3] |
436 |
1 |
|
T17 |
17 |
|
T18 |
10 |
|
T21 |
13 |
| false |
120 |
1 |
|
T17 |
4 |
|
T18 |
5 |
|
T21 |
3 |
| true |
3327 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10116 |
1 |
|
T3 |
3 |
|
T17 |
27 |
|
T18 |
20 |
| others[1] |
826 |
1 |
|
T3 |
1 |
|
T17 |
14 |
|
T18 |
18 |
| others[2] |
728 |
1 |
|
T3 |
3 |
|
T17 |
21 |
|
T18 |
18 |
| others[3] |
1342 |
1 |
|
T3 |
4 |
|
T16 |
1 |
|
T17 |
26 |
| false |
404 |
1 |
|
T3 |
2 |
|
T17 |
13 |
|
T18 |
12 |
| true |
501 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10078 |
1 |
|
T3 |
3 |
|
T17 |
17 |
|
T18 |
17 |
| others[1] |
761 |
1 |
|
T3 |
5 |
|
T17 |
23 |
|
T18 |
22 |
| others[2] |
776 |
1 |
|
T3 |
1 |
|
T17 |
17 |
|
T18 |
17 |
| others[3] |
1325 |
1 |
|
T3 |
4 |
|
T17 |
32 |
|
T18 |
35 |
| false |
460 |
1 |
|
T16 |
1 |
|
T17 |
12 |
|
T18 |
10 |
| true |
517 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2424 |
1 |
|
T3 |
2 |
|
T17 |
14 |
|
T18 |
8 |
| others[1] |
2438 |
1 |
|
T3 |
4 |
|
T17 |
6 |
|
T18 |
12 |
| others[2] |
2356 |
1 |
|
T3 |
3 |
|
T17 |
10 |
|
T18 |
9 |
| others[3] |
3902 |
1 |
|
T3 |
1 |
|
T17 |
8 |
|
T18 |
20 |
| false |
1215 |
1 |
|
T3 |
3 |
|
T16 |
1 |
|
T17 |
14 |
| true |
1582 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9536 |
1 |
|
T17 |
11 |
|
T18 |
6 |
|
T39 |
1 |
| others[1] |
266 |
1 |
|
T4 |
1 |
|
T17 |
19 |
|
T18 |
6 |
| others[2] |
289 |
1 |
|
T17 |
8 |
|
T18 |
12 |
|
T21 |
2 |
| others[3] |
435 |
1 |
|
T17 |
12 |
|
T6 |
1 |
|
T18 |
13 |
| false |
160 |
1 |
|
T17 |
7 |
|
T18 |
6 |
|
T21 |
10 |
| true |
3231 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9725 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
6 |
| others[1] |
484 |
1 |
|
T3 |
1 |
|
T17 |
17 |
|
T18 |
10 |
| others[2] |
460 |
1 |
|
T3 |
3 |
|
T17 |
11 |
|
T18 |
11 |
| others[3] |
758 |
1 |
|
T3 |
1 |
|
T17 |
10 |
|
T18 |
21 |
| false |
250 |
1 |
|
T17 |
5 |
|
T18 |
2 |
|
T21 |
5 |
| true |
2240 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9564 |
1 |
|
T17 |
12 |
|
T18 |
7 |
|
T19 |
1 |
| others[1] |
249 |
1 |
|
T17 |
14 |
|
T6 |
1 |
|
T18 |
7 |
| others[2] |
265 |
1 |
|
T16 |
1 |
|
T17 |
10 |
|
T18 |
7 |
| others[3] |
469 |
1 |
|
T4 |
1 |
|
T17 |
16 |
|
T18 |
20 |
| false |
140 |
1 |
|
T17 |
7 |
|
T18 |
5 |
|
T21 |
2 |
| true |
3230 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T17 |
42 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9531 |
1 |
|
T4 |
1 |
|
T17 |
12 |
|
T18 |
12 |
| others[1] |
269 |
1 |
|
T17 |
18 |
|
T18 |
12 |
|
T21 |
11 |
| others[2] |
265 |
1 |
|
T16 |
1 |
|
T17 |
10 |
|
T18 |
10 |
| others[3] |
432 |
1 |
|
T17 |
12 |
|
T18 |
11 |
|
T39 |
1 |
| false |
126 |
1 |
|
T17 |
7 |
|
T18 |
7 |
|
T21 |
3 |
| true |
3294 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T17 |
42 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10099 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
21 |
| others[1] |
816 |
1 |
|
T3 |
3 |
|
T17 |
21 |
|
T18 |
17 |
| others[2] |
800 |
1 |
|
T3 |
4 |
|
T17 |
19 |
|
T18 |
25 |
| others[3] |
1320 |
1 |
|
T3 |
2 |
|
T17 |
27 |
|
T18 |
27 |
| false |
379 |
1 |
|
T3 |
3 |
|
T17 |
13 |
|
T18 |
3 |
| true |
503 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10040 |
1 |
|
T3 |
3 |
|
T16 |
1 |
|
T17 |
19 |
| others[1] |
748 |
1 |
|
T3 |
2 |
|
T17 |
21 |
|
T18 |
17 |
| others[2] |
802 |
1 |
|
T3 |
5 |
|
T17 |
16 |
|
T18 |
20 |
| others[3] |
1391 |
1 |
|
T3 |
2 |
|
T17 |
37 |
|
T18 |
31 |
| false |
422 |
1 |
|
T3 |
1 |
|
T17 |
8 |
|
T18 |
13 |
| true |
514 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2430 |
1 |
|
T3 |
2 |
|
T17 |
7 |
|
T18 |
11 |
| others[1] |
2378 |
1 |
|
T3 |
3 |
|
T17 |
10 |
|
T18 |
5 |
| others[2] |
2409 |
1 |
|
T3 |
5 |
|
T17 |
11 |
|
T18 |
7 |
| others[3] |
3957 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T17 |
14 |
| false |
1188 |
1 |
|
T3 |
1 |
|
T17 |
2 |
|
T18 |
2 |
| true |
1555 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
57 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9557 |
1 |
|
T17 |
10 |
|
T18 |
11 |
|
T19 |
1 |
| others[1] |
279 |
1 |
|
T17 |
10 |
|
T18 |
15 |
|
T21 |
11 |
| others[2] |
260 |
1 |
|
T17 |
11 |
|
T18 |
8 |
|
T34 |
1 |
| others[3] |
442 |
1 |
|
T17 |
12 |
|
T18 |
12 |
|
T7 |
1 |
| false |
159 |
1 |
|
T17 |
8 |
|
T18 |
5 |
|
T21 |
8 |
| true |
3220 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9729 |
1 |
|
T17 |
12 |
|
T18 |
9 |
|
T22 |
3 |
| others[1] |
509 |
1 |
|
T3 |
3 |
|
T17 |
6 |
|
T18 |
6 |
| others[2] |
453 |
1 |
|
T17 |
9 |
|
T18 |
8 |
|
T11 |
1 |
| others[3] |
784 |
1 |
|
T3 |
2 |
|
T17 |
19 |
|
T18 |
12 |
| false |
249 |
1 |
|
T4 |
1 |
|
T17 |
2 |
|
T18 |
4 |
| true |
2193 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9544 |
1 |
|
T16 |
1 |
|
T17 |
11 |
|
T18 |
8 |
| others[1] |
254 |
1 |
|
T4 |
1 |
|
T17 |
16 |
|
T18 |
10 |
| others[2] |
251 |
1 |
|
T17 |
7 |
|
T18 |
8 |
|
T39 |
1 |
| others[3] |
440 |
1 |
|
T17 |
21 |
|
T6 |
1 |
|
T18 |
19 |
| false |
117 |
1 |
|
T17 |
2 |
|
T18 |
3 |
|
T21 |
4 |
| true |
3311 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T17 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9559 |
1 |
|
T17 |
16 |
|
T18 |
9 |
|
T46 |
125 |
| others[1] |
219 |
1 |
|
T17 |
6 |
|
T18 |
8 |
|
T21 |
8 |
| others[2] |
264 |
1 |
|
T16 |
1 |
|
T17 |
15 |
|
T18 |
6 |
| others[3] |
456 |
1 |
|
T17 |
16 |
|
T18 |
19 |
|
T21 |
25 |
| false |
139 |
1 |
|
T17 |
9 |
|
T18 |
6 |
|
T21 |
4 |
| true |
3280 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10079 |
1 |
|
T3 |
3 |
|
T17 |
22 |
|
T18 |
20 |
| others[1] |
773 |
1 |
|
T3 |
2 |
|
T17 |
12 |
|
T6 |
1 |
| others[2] |
799 |
1 |
|
T3 |
4 |
|
T17 |
25 |
|
T18 |
20 |
| others[3] |
1352 |
1 |
|
T3 |
4 |
|
T16 |
1 |
|
T17 |
38 |
| false |
421 |
1 |
|
T2 |
1 |
|
T17 |
4 |
|
T18 |
9 |
| true |
493 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T11 |
2 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |