Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	225642	1		T1	402		T2	2		T3	9
auto[FlashEraseBank]	253393	1		T3	4		T4	7		T17	1042

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	264228	1		T1	10		T3	4		T17	574
auto[FlashOpProgram]	195233	1		T1	384		T3	7		T4	36
auto[FlashOpErase]	15574	1		T1	8		T2	2		T3	2
auto[FlashOpInvalid]	4000	1		T43	200		T106	200		T204	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	264228	1		T1	10		T3	4		T17	574
op[FlashOpProgram]	195233	1		T1	384		T3	7		T4	36
op[FlashOpErase]	15574	1		T1	8		T2	2		T3	2
read_erase_read	766	1		T3	1		T17	7		T18	13
read_prog_read	1161	1		T17	1		T18	5		T19	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	339881	1		T3	13		T4	30		T17	94
auto[FlashPartInfo]	135410	1		T1	402		T2	2		T4	6
auto[FlashPartInfo1]	868	1		T6	12		T39	2		T34	11
auto[FlashPartInfo2]	2876	1		T6	28		T39	12		T34	22

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	200500	1		T3	4		T17	30		T6	768
auto[FlashPartData]	auto[FlashOpProgram]	131722	1		T3	7		T4	30		T17	35
auto[FlashPartData]	auto[FlashOpErase]	3745	1		T3	2		T17	29		T18	40
auto[FlashPartData]	auto[FlashOpInvalid]	3914	1		T43	198		T106	194		T204	196
auto[FlashPartInfo]	auto[FlashOpRead]	61368	1		T1	10		T17	544		T6	127
auto[FlashPartInfo]	auto[FlashOpProgram]	62181	1		T1	384		T4	6		T17	484
auto[FlashPartInfo]	auto[FlashOpErase]	11793	1		T1	8		T2	2		T17	20
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T43	2		T106	4		T204	4
auto[FlashPartInfo1]	auto[FlashOpRead]	702	1		T6	12		T39	2		T34	11
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T84	32		T87	32		T90	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T75	1		T379	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T379	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1658	1		T6	28		T39	12		T34	22
auto[FlashPartInfo2]	auto[FlashOpProgram]	1168	1		T21	1		T37	6		T52	5
auto[FlashPartInfo2]	auto[FlashOpErase]	34	1		T21	1		T95	19		T106	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T106	2		T380	2		T381	2