Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
evic_cfg_cp 4 0 4 100.00 100 1 1 4
evic_idx_cp 4 0 4 100.00 100 1 1 0
evic_op_cp 2 0 2 100.00 100 1 1 0


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
evic_all_cross 32 0 32 100.00 100 1 1 0


Summary for Variable evic_cfg_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for evic_cfg_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29801 1 T3 8 T17 16 T18 28
auto[1] 129 1 T94 35 T27 1 T382 5
auto[2] 123 1 T19 1 T120 8 T383 16
auto[3] 254 1 T25 11 T111 90 T99 1



Summary for Variable evic_idx_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for evic_idx_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
evic_idx[0] 7630 1 T3 2 T17 4 T18 7
evic_idx[1] 7585 1 T3 2 T17 4 T18 7
evic_idx[2] 7544 1 T3 2 T17 4 T18 7
evic_idx[3] 7548 1 T3 2 T17 4 T18 7



Summary for Variable evic_op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for evic_op_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
evic_op[1] 29267 1 T17 4 T46 372 T49 320
evic_op[2] 424 1 T17 4 T19 1 T75 8



Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for evic_all_cross

Bins
evic_idx_cpevic_op_cpevic_cfg_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
evic_idx[0] evic_op[1] auto[0] 7235 1 T17 1 T46 93 T49 80
evic_idx[0] evic_op[1] auto[1] 39 1 T94 10 T382 1 T187 23
evic_idx[0] evic_op[1] auto[2] 11 1 T383 11 - - - -
evic_idx[0] evic_op[1] auto[3] 79 1 T25 5 T111 30 T382 6
evic_idx[0] evic_op[2] auto[0] 73 1 T17 1 T75 2 T110 4
evic_idx[0] evic_op[2] auto[1] 2 1 T167 1 T384 1 - -
evic_idx[0] evic_op[2] auto[2] 24 1 T385 2 T386 5 T387 6
evic_idx[0] evic_op[2] auto[3] 13 1 T189 1 T388 1 T389 1
evic_idx[1] evic_op[1] auto[0] 7233 1 T17 1 T46 93 T49 80
evic_idx[1] evic_op[1] auto[1] 41 1 T94 13 T382 1 T187 15
evic_idx[1] evic_op[1] auto[2] 3 1 T383 3 - - - -
evic_idx[1] evic_op[1] auto[3] 45 1 T25 1 T111 26 T382 5
evic_idx[1] evic_op[2] auto[0] 67 1 T17 1 T75 2 T110 4
evic_idx[1] evic_op[2] auto[1] 2 1 T384 1 T390 1 - -
evic_idx[1] evic_op[2] auto[2] 27 1 T385 1 T386 5 T387 10
evic_idx[1] evic_op[2] auto[3] 13 1 T274 1 T391 1 T388 1
evic_idx[2] evic_op[1] auto[0] 7232 1 T17 1 T46 93 T49 80
evic_idx[2] evic_op[1] auto[1] 22 1 T94 7 T382 1 T187 8
evic_idx[2] evic_op[1] auto[2] 1 1 T383 1 - - - -
evic_idx[2] evic_op[1] auto[3] 41 1 T25 4 T111 19 T382 3
evic_idx[2] evic_op[2] auto[0] 61 1 T17 1 T75 2 T110 4
evic_idx[2] evic_op[2] auto[1] 3 1 T27 1 T167 1 T318 1
evic_idx[2] evic_op[2] auto[2] 18 1 T19 1 T386 6 T387 5
evic_idx[2] evic_op[2] auto[3] 12 1 T392 1 T393 1 T394 1
evic_idx[3] evic_op[1] auto[0] 7233 1 T17 1 T46 93 T49 80
evic_idx[3] evic_op[1] auto[1] 16 1 T94 5 T382 2 T187 6
evic_idx[3] evic_op[1] auto[2] 1 1 T383 1 - - - -
evic_idx[3] evic_op[1] auto[3] 35 1 T25 1 T111 15 T382 5
evic_idx[3] evic_op[2] auto[0] 67 1 T17 1 T75 2 T110 4
evic_idx[3] evic_op[2] auto[1] 4 1 T167 1 T318 1 T395 1
evic_idx[3] evic_op[2] auto[2] 22 1 T385 1 T386 7 T387 6
evic_idx[3] evic_op[2] auto[3] 16 1 T99 1 T392 1 T394 1

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