Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5068 | 
1 | 
 | 
T11 | 
1 | 
 | 
T22 | 
124 | 
 | 
T50 | 
126 | 
| instr_types[0] | 
6182 | 
1 | 
 | 
T22 | 
173 | 
 | 
T50 | 
162 | 
 | 
T51 | 
233 | 
| instr_types[1] | 
4620594 | 
1 | 
 | 
T3 | 
170 | 
 | 
T5 | 
10 | 
 | 
T6 | 
15999 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4629996 | 
1 | 
 | 
T3 | 
170 | 
 | 
T5 | 
10 | 
 | 
T6 | 
15999 | 
| auto[1] | 
1848 | 
1 | 
 | 
T22 | 
140 | 
 | 
T50 | 
255 | 
 | 
T51 | 
200 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4635 | 
1 | 
 | 
T11 | 
1 | 
 | 
T22 | 
81 | 
 | 
T50 | 
90 | 
| auto[0] | 
instr_types[0] | 
5551 | 
1 | 
 | 
T22 | 
111 | 
 | 
T50 | 
106 | 
 | 
T51 | 
196 | 
| auto[0] | 
instr_types[1] | 
4619810 | 
1 | 
 | 
T3 | 
170 | 
 | 
T5 | 
10 | 
 | 
T6 | 
15999 | 
| auto[1] | 
others | 
433 | 
1 | 
 | 
T22 | 
43 | 
 | 
T50 | 
36 | 
 | 
T51 | 
44 | 
| auto[1] | 
instr_types[0] | 
631 | 
1 | 
 | 
T22 | 
62 | 
 | 
T50 | 
56 | 
 | 
T51 | 
37 | 
| auto[1] | 
instr_types[1] | 
784 | 
1 | 
 | 
T22 | 
35 | 
 | 
T50 | 
163 | 
 | 
T51 | 
119 |