Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	59122	1		T34	9529		T183	2551		T327	9172
rd_lvl[2]	39069	1		T7	1739		T34	5507		T183	1513
rd_lvl[3]	11730	1		T7	1530		T34	1		T183	786
rd_lvl[4]	31756	1		T7	430		T196	1894		T328	2560
rd_lvl[5]	25272	1		T7	1373		T196	1264		T328	1256
rd_lvl[6]	14650	1		T7	1788		T196	306		T328	1
rd_lvl[7]	19473	1		T6	997		T196	321		T183	767
rd_lvl[8]	20565	1		T6	775		T196	595		T183	766
rd_lvl[9]	8385	1		T6	94		T183	1069		T329	402
rd_lvl[10]	4730	1		T6	4		T183	464		T330	645
rd_lvl[11]	6091	1		T7	1		T119	570		T183	88
rd_lvl[12]	7131	1		T7	13		T32	582		T119	318
rd_lvl[13]	4084	1		T7	12		T32	518		T33	296
rd_lvl[14]	5026	1		T118	544		T183	88		T275	587
rd_lvl[15]	4878	1		T31	553		T32	73		T118	217