Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	390967	1		T1	2		T2	2		T3	2
all_pins[1]	390967	1		T1	2		T2	2		T3	2
all_pins[2]	390967	1		T1	2		T2	2		T3	2
all_pins[3]	390967	1		T1	2		T2	2		T3	2
all_pins[4]	390967	1		T1	2		T2	2		T3	2
all_pins[5]	390967	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1974712	1		T1	12		T2	12		T3	12
values[0x1]	371090	1		T6	2836		T7	8044		T34	16414
transitions[0x0=>0x1]	336289	1		T6	2801		T7	7017		T34	15037
transitions[0x1=>0x0]	336269	1		T6	2801		T7	7017		T34	15037

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	390809	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	158	1		T258	3		T259	2		T260	3
all_pins[0]	transitions[0x0=>0x1]	78	1		T258	1		T259	2		T320	2
all_pins[0]	transitions[0x1=>0x0]	89	1		T258	1		T260	2		T320	2
all_pins[1]	values[0x0]	390798	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	169	1		T258	3		T260	5		T320	5
all_pins[1]	transitions[0x0=>0x1]	139	1		T258	3		T260	5		T320	4
all_pins[1]	transitions[0x1=>0x0]	1646	1		T31	505		T275	50		T311	426
all_pins[2]	values[0x0]	389291	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	1676	1		T31	505		T275	50		T311	426
all_pins[2]	transitions[0x0=>0x1]	42	1		T259	2		T320	1		T321	2
all_pins[2]	transitions[0x1=>0x0]	262007	1		T6	1870		T7	6886		T34	15037
all_pins[3]	values[0x0]	127326	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	263641	1		T6	1870		T7	6886		T34	15037
all_pins[3]	transitions[0x0=>0x1]	230647	1		T6	1835		T7	5859		T34	13660
all_pins[3]	transitions[0x1=>0x0]	72372	1		T6	931		T7	131		T23	935
all_pins[4]	values[0x0]	285601	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	105366	1		T6	966		T7	1158		T34	1377
all_pins[4]	transitions[0x0=>0x1]	105343	1		T6	966		T7	1158		T34	1377
all_pins[4]	transitions[0x1=>0x0]	57	1		T260	2		T320	1		T321	3
all_pins[5]	values[0x0]	390887	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	80	1		T260	2		T320	3		T321	3
all_pins[5]	transitions[0x0=>0x1]	40	1		T260	1		T320	2		T321	2
all_pins[5]	transitions[0x1=>0x0]	98	1		T258	2		T259	1		T260	1