Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 275 1 T258 4 T259 4 T260 4
all_values[1] 275 1 T258 4 T259 4 T260 4
all_values[2] 275 1 T258 4 T259 4 T260 4
all_values[3] 275 1 T258 4 T259 4 T260 4
all_values[4] 275 1 T258 4 T259 4 T260 4
all_values[5] 275 1 T258 4 T259 4 T260 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 878 1 T258 10 T259 14 T260 11
auto[1] 772 1 T258 14 T259 10 T260 13



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 545 1 T258 10 T259 10 T260 9
auto[1] 1105 1 T258 14 T259 14 T260 15



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 972 1 T258 14 T259 19 T260 16
auto[1] 678 1 T258 10 T259 5 T260 8



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 89 1 T259 2 T260 2 T320 4
all_values[0] auto[0] auto[1] auto[1] 69 1 T258 1 T259 1 T260 1
all_values[0] auto[1] auto[0] auto[1] 65 1 T258 1 T259 1 T260 1
all_values[0] auto[1] auto[1] auto[1] 52 1 T258 2 T321 3 T322 1
all_values[1] auto[0] auto[0] auto[1] 83 1 T258 1 T259 4 T321 2
all_values[1] auto[0] auto[1] auto[1] 84 1 T258 1 T260 2 T320 3
all_values[1] auto[1] auto[0] auto[1] 62 1 T320 3 T321 1 T323 1
all_values[1] auto[1] auto[1] auto[1] 46 1 T258 2 T260 2 T320 1
all_values[2] auto[0] auto[0] auto[0] 93 1 T258 3 T259 1 T260 2
all_values[2] auto[0] auto[1] auto[0] 75 1 T258 1 T260 2 T320 1
all_values[2] auto[1] auto[0] auto[1] 52 1 T259 1 T320 2 T321 1
all_values[2] auto[1] auto[1] auto[1] 55 1 T259 2 T320 1 T321 1
all_values[3] auto[0] auto[0] auto[0] 94 1 T258 2 T259 3 T260 2
all_values[3] auto[0] auto[1] auto[0] 65 1 T259 1 T260 1 T320 3
all_values[3] auto[1] auto[0] auto[1] 58 1 T258 1 T320 1 T321 1
all_values[3] auto[1] auto[1] auto[1] 58 1 T258 1 T260 1 T320 2
all_values[4] auto[0] auto[0] auto[0] 57 1 T258 1 T320 1 T321 3
all_values[4] auto[0] auto[0] auto[1] 25 1 T260 1 T322 1 T324 2
all_values[4] auto[0] auto[1] auto[0] 55 1 T258 1 T259 1 T320 2
all_values[4] auto[0] auto[1] auto[1] 26 1 T259 2 T320 1 T321 1
all_values[4] auto[1] auto[0] auto[1] 55 1 T259 1 T260 3 T320 2
all_values[4] auto[1] auto[1] auto[1] 57 1 T258 2 T320 1 T321 1
all_values[5] auto[0] auto[0] auto[0] 62 1 T259 1 T321 3 T323 2
all_values[5] auto[0] auto[0] auto[1] 22 1 T322 1 T325 1 T326 1
all_values[5] auto[0] auto[1] auto[0] 44 1 T258 2 T259 3 T260 2
all_values[5] auto[0] auto[1] auto[1] 29 1 T258 1 T260 1 T320 1
all_values[5] auto[1] auto[0] auto[1] 61 1 T258 1 T320 4 T321 1
all_values[5] auto[1] auto[1] auto[1] 57 1 T260 1 T320 1 T321 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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