Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 26803917 1 T1 832 T2 730 T3 3005
full_word 7855593 1 T1 229 T2 648 T3 923


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 34659210 1 T1 1061 T2 1378 T3 3928
auto[TlIntgErrCmd] 104 1 T59 3 T203 6 T206 9
auto[TlIntgErrData] 107 1 T59 2 T203 7 T206 3
auto[TlIntgErrBoth] 89 1 T59 5 T203 7 T206 8


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30209877 1 T1 851 T2 1314 T3 3081
auto[1] 4449633 1 T1 210 T2 64 T3 847


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 26138989 1 T1 799 T2 721 T3 2931
auto[TlIntgErrNone] partial auto[1] 664653 1 T1 33 T2 9 T3 74
auto[TlIntgErrNone] full_word auto[0] 4070743 1 T1 52 T2 593 T3 150
auto[TlIntgErrNone] full_word auto[1] 3784825 1 T1 177 T2 55 T3 773
auto[TlIntgErrCmd] partial auto[0] 53 1 T59 2 T203 4 T206 3
auto[TlIntgErrCmd] partial auto[1] 44 1 T59 1 T203 2 T206 6
auto[TlIntgErrCmd] full_word auto[0] 4 1 T288 1 T259 1 T343 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T339 1 T343 1 T344 1
auto[TlIntgErrData] partial auto[0] 50 1 T59 1 T203 4 T206 2
auto[TlIntgErrData] partial auto[1] 47 1 T59 1 T203 3 T206 1
auto[TlIntgErrData] full_word auto[0] 3 1 T251 1 T345 1 T340 1
auto[TlIntgErrData] full_word auto[1] 7 1 T288 1 T255 1 T259 1
auto[TlIntgErrBoth] partial auto[0] 30 1 T59 4 T203 3 T206 2
auto[TlIntgErrBoth] partial auto[1] 51 1 T59 1 T203 4 T206 6
auto[TlIntgErrBoth] full_word auto[0] 5 1 T249 1 T255 1 T259 1
auto[TlIntgErrBoth] full_word auto[1] 3 1 T345 1 T340 1 T343 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 19097 1 T59 10 T60 51 T171 366
full_word 4469958 1 T1 96 T3 70 T6 16494


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4488769 1 T1 96 T3 70 T6 16494
auto[TlIntgErrCmd] 86 1 T59 5 T203 5 T206 8
auto[TlIntgErrData] 104 1 T59 1 T203 7 T206 7
auto[TlIntgErrBoth] 96 1 T59 4 T203 8 T206 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4463102 1 T1 96 T3 70 T6 16494
auto[1] 25953 1 T59 6 T60 63 T171 466


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1370 1 T60 4 T171 43 T202 24
auto[TlIntgErrNone] partial auto[1] 17465 1 T60 47 T171 323 T202 422
auto[TlIntgErrNone] full_word auto[0] 4461610 1 T1 96 T3 70 T6 16494
auto[TlIntgErrNone] full_word auto[1] 8324 1 T60 16 T171 143 T202 235
auto[TlIntgErrCmd] partial auto[0] 25 1 T59 1 T206 1 T249 2
auto[TlIntgErrCmd] partial auto[1] 54 1 T59 4 T203 5 T206 6
auto[TlIntgErrCmd] full_word auto[0] 4 1 T206 1 T259 1 T342 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T255 1 T256 1 T346 1
auto[TlIntgErrData] partial auto[0] 47 1 T59 1 T203 3 T206 2
auto[TlIntgErrData] partial auto[1] 49 1 T203 4 T206 5 T249 3
auto[TlIntgErrData] full_word auto[0] 3 1 T249 1 T259 1 T347 1
auto[TlIntgErrData] full_word auto[1] 5 1 T251 1 T289 2 T345 1
auto[TlIntgErrBoth] partial auto[0] 41 1 T59 2 T203 4 T206 2
auto[TlIntgErrBoth] partial auto[1] 46 1 T59 2 T203 4 T206 2
auto[TlIntgErrBoth] full_word auto[0] 2 1 T256 1 T345 1 - -
auto[TlIntgErrBoth] full_word auto[1] 7 1 T288 1 T255 1 T256 1

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