Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	98.41	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

315 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.num	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.op	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.start	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr10.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr11.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr12.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1666	1		T59	10		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	958	1		T239	5		T240	6		T241	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1306	1		T239	8		T240	8		T241	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1326	1		T239	8		T240	8		T241	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	914	1		T239	8		T240	7		T241	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1104	1		T239	8		T240	4		T241	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	917	1		T239	4		T240	8		T241	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	35	1		T239	7		T240	7		T241	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1216	1		T160	5		T166	3		T167	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	984	1		T160	8		T166	5		T167	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	570	1		T59	2		T60	1		T61	2
auto[1]	975	1		T59	6		T236	1		T237	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	727	1		T59	3		T61	1		T236	1
auto[1]	1011	1		T59	4		T236	1		T237	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	632	1		T59	2		T60	1		T61	2
auto[1]	984	1		T59	7		T237	1		T205	64

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	536	1		T59	3		T60	1		T61	2
auto[1]	963	1		T59	7		T236	1		T237	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	667	1		T59	3		T60	1		T61	2
auto[1]	920	1		T59	7		T236	1		T237	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	697	1		T59	3		T60	1		T61	2
auto[1]	1012	1		T59	7		T236	1		T237	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	599	1		T59	2		T60	1		T61	1
auto[1]	978	1		T59	7		T236	1		T237	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	472	1		T59	1		T60	1		T61	1
auto[1]	756	1		T59	7		T61	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	622	1		T59	1		T60	1		T61	1
auto[1]	790	1		T59	8		T61	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	531	1		T59	1		T60	1		T61	1
auto[1]	770	1		T59	9		T61	1		T236	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	437	1		T59	1		T60	1		T61	1
auto[1]	750	1		T59	9		T61	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	569	1		T59	1		T60	1		T61	1
auto[1]	775	1		T59	8		T61	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	604	1		T59	1		T60	1		T61	1
auto[1]	783	1		T59	9		T61	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	504	1		T59	1		T60	1		T61	1
auto[1]	763	1		T59	9		T61	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	639	1		T59	5		T171	1		T205	88
auto[1]	786	1		T59	5		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	839	1		T59	5		T236	1		T205	128
auto[1]	782	1		T59	4		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	723	1		T59	5		T236	1		T171	1
auto[1]	633	1		T59	5		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	604	1		T59	5		T236	1		T171	1
auto[1]	782	1		T59	4		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	761	1		T59	5		T236	1		T171	1
auto[1]	786	1		T59	5		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	799	1		T59	4		T236	1		T171	1
auto[1]	627	1		T59	4		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	680	1		T59	5		T205	96		T203	5
auto[1]	726	1		T59	5		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	385	1		T59	1		T61	1		T205	88
auto[1]	1062	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	590	1		T59	1		T61	1		T205	128
auto[1]	1063	1		T59	8		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	467	1		T59	1		T61	1		T205	104
auto[1]	1059	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	350	1		T59	1		T61	1		T205	80
auto[1]	1065	1		T59	8		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	508	1		T59	1		T61	1		T205	112
auto[1]	994	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	547	1		T59	1		T61	1		T205	120
auto[1]	1060	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	430	1		T59	1		T61	1		T205	96
auto[1]	1062	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	326	1		T61	1		T205	24		T242	69
auto[1]	937	1		T59	9		T61	1		T236	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	484	1		T61	1		T205	64		T242	69
auto[1]	746	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	380	1		T59	1		T61	1		T205	40
auto[1]	956	1		T59	8		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	290	1		T59	1		T61	1		T205	16
auto[1]	699	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	420	1		T59	1		T61	1		T205	48
auto[1]	957	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	456	1		T59	1		T61	1		T205	56
auto[1]	965	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	359	1		T59	1		T61	1		T205	32
auto[1]	941	1		T59	9		T60	1		T61	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	478	1		T59	3		T236	1		T205	24
auto[1]	805	1		T59	7		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	673	1		T59	3		T236	1		T205	64
auto[1]	807	1		T59	7		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	557	1		T59	3		T236	1		T205	40
auto[1]	797	1		T59	6		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	434	1		T59	3		T236	1		T205	16
auto[1]	796	1		T59	7		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	598	1		T59	3		T236	1		T205	48
auto[1]	805	1		T59	6		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	635	1		T59	3		T236	1		T205	56
auto[1]	809	1		T59	7		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	514	1		T59	3		T236	1		T205	32
auto[1]	771	1		T59	7		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	278	1		T59	3		T61	2		T236	1
auto[1]	842	1		T59	7		T60	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	414	1		T59	3		T61	2		T236	1
auto[1]	882	1		T59	7		T60	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	343	1		T59	2		T61	2		T236	1
auto[1]	855	1		T59	7		T60	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	218	1		T59	3		T61	2		T236	1
auto[1]	832	1		T59	7		T60	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	374	1		T59	3		T61	2		T236	1
auto[1]	867	1		T59	7		T60	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	406	1		T59	3		T61	2		T236	1
auto[1]	873	1		T59	6		T60	1		T236	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	306	1		T59	2		T61	2		T171	1
auto[1]	856	1		T59	6		T60	1		T236	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	383	1		T59	2		T205	24		T203	1
auto[1]	868	1		T59	7		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	583	1		T59	2		T205	64		T203	1
auto[1]	865	1		T59	7		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	438	1		T59	2		T205	40		T203	1
auto[1]	899	1		T59	6		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	335	1		T59	2		T205	16		T203	1
auto[1]	870	1		T59	8		T60	1		T61	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	502	1		T59	2		T205	48		T203	1
auto[1]	871	1		T59	8		T60	1		T61	2