Unified Coverage Report :: Module :: flash_phy_rd_buf_dep

Module : flash_phy_rd_buf_dep

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	100.00	90.60			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.53	100.00	90.14			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Module : flash_phy_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T6

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Branch Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T6
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	815182952	7371673	0	0
BufferDepRsp_A	815182952	813519130	0	0
BufferIncrOverFlow_A	815182952	7371682	0	0
DepBufferRspOrder_A	815182953	16624748	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815182952	7371673	0	0
T1	6962	144	0	0
T2	770052	0	0	0
T3	43822	191	0	0
T4	877846	0	0	0
T5	651650	4192	0	0
T6	244842	35034	0	0
T7	17648	278	0	0
T11	6866	0	0	0
T16	3214	0	0	0
T17	4244	0	0	0
T18	0	50844	0	0
T19	0	581	0	0
T21	0	2654	0	0
T24	0	4224	0	0
T27	0	86	0	0
T32	0	1024	0	0
T33	0	1024	0	0
T43	0	23923	0	0
T53	0	11587	0	0
T78	0	26	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815182952	813519130	0	0
T1	6962	6844	0	0
T2	770052	770026	0	0
T3	43822	41726	0	0
T4	877846	877834	0	0
T5	651650	625452	0	0
T6	244842	244576	0	0
T7	17648	12222	0	0
T11	6866	5340	0	0
T16	3214	3086	0	0
T17	4244	3928	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815182952	7371682	0	0
T1	6962	144	0	0
T2	770052	0	0	0
T3	43822	191	0	0
T4	877846	0	0	0
T5	651650	4192	0	0
T6	244842	35034	0	0
T7	17648	278	0	0
T11	6866	0	0	0
T16	3214	0	0	0
T17	4244	0	0	0
T18	0	50844	0	0
T19	0	581	0	0
T21	0	2654	0	0
T24	0	4224	0	0
T27	0	86	0	0
T32	0	1024	0	0
T33	0	1024	0	0
T43	0	23923	0	0
T53	0	11587	0	0
T78	0	26	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815182953	16624748	0	0
T1	6962	176	0	0
T2	770052	263744	0	0
T3	43822	671	0	0
T4	877846	32	0	0
T5	651650	9792	0	0
T6	244842	35074	0	0
T7	17648	438	0	0
T11	6866	57	0	0
T16	3214	32	0	0
T17	4244	64	0	0
T18	0	25126	0	0
T19	0	581	0	0
T21	0	2654	0	0
T26	0	131072	0	0
T43	0	23923	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T6

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T6
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	407591476	4259637	0	0
BufferDepRsp_A	407591476	406759565	0	0
BufferIncrOverFlow_A	407591476	4259643	0	0
DepBufferRspOrder_A	407591476	9213157	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	4259637	0	0
T1	3481	69	0	0
T2	385026	0	0	0
T3	21911	128	0	0
T4	438923	0	0	0
T5	325825	4192	0	0
T6	122421	19754	0	0
T7	8824	103	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	25718	0	0
T24	0	4224	0	0
T27	0	86	0	0
T32	0	1024	0	0
T33	0	1024	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	4259643	0	0
T1	3481	69	0	0
T2	385026	0	0	0
T3	21911	128	0	0
T4	438923	0	0	0
T5	325825	4192	0	0
T6	122421	19754	0	0
T7	8824	103	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	25718	0	0
T24	0	4224	0	0
T27	0	86	0	0
T32	0	1024	0	0
T33	0	1024	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	9213157	0	0
T1	3481	101	0	0
T2	385026	132672	0	0
T3	21911	608	0	0
T4	438923	32	0	0
T5	325825	9792	0	0
T6	122421	19794	0	0
T7	8824	263	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	64	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T26,T121
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T19
1	1	Covered	T1,T3,T6

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T6
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	407591476	3112036	0	0
BufferDepRsp_A	407591476	406759565	0	0
BufferIncrOverFlow_A	407591476	3112039	0	0
DepBufferRspOrder_A	407591477	7411591	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	3112036	0	0
T1	3481	75	0	0
T2	385026	0	0	0
T3	21911	63	0	0
T4	438923	0	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	25126	0	0
T19	0	581	0	0
T21	0	2654	0	0
T43	0	23923	0	0
T53	0	11587	0	0
T78	0	26	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	3112039	0	0
T1	3481	75	0	0
T2	385026	0	0	0
T3	21911	63	0	0
T4	438923	0	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	25126	0	0
T19	0	581	0	0
T21	0	2654	0	0
T43	0	23923	0	0
T53	0	11587	0	0
T78	0	26	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591477	7411591	0	0
T1	3481	75	0	0
T2	385026	131072	0	0
T3	21911	63	0	0
T4	438923	0	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	25126	0	0
T19	0	581	0	0
T21	0	2654	0	0
T26	0	131072	0	0
T43	0	23923	0	0