Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1630365904	1627038260	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1630365904	454311833	0	0
GntImpliesValid_A	1630365904	454311833	0	0
GrantKnown_A	1630365904	1627038260	0	0
IdxKnown_A	1630365904	1627038260	0	0
IndexIsCorrect_A	1630365904	454311833	0	0
NoReadyValidNoGrant_A	1630365904	176596399	0	0
Priority_A	1630365904	478489498	0	0
ReadyAndValidImplyGrant_A	1630365904	454311833	0	0
ReqAndReadyImplyGrant_A	1630365904	454311833	0	0
ReqImpliesValid_A	1630365904	478489498	0	0
ValidKnown_A	1630365904	1627038260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	1627038260	0	0
T1	13924	13688	0	0
T2	1540104	1540052	0	0
T3	87644	83452	0	0
T4	1755692	1755668	0	0
T5	1303300	1250904	0	0
T6	489684	489152	0	0
T7	35296	24444	0	0
T11	13732	10680	0	0
T16	6428	6172	0	0
T17	8488	7856	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	454311833	0	0
T1	13924	3202	0	0
T2	1540104	514650	0	0
T3	87644	12120	0	0
T4	1755692	872912	0	0
T5	1303300	231958	0	0
T6	489684	70148	0	0
T7	35296	1006	0	0
T11	13732	114	0	0
T16	6428	64	0	0
T17	8488	148	0	0
T18	0	105940	0	0
T19	0	1162	0	0
T26	0	255794	0	0
T42	0	1432	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	454311833	0	0
T1	13924	3202	0	0
T2	1540104	514650	0	0
T3	87644	12120	0	0
T4	1755692	872912	0	0
T5	1303300	231958	0	0
T6	489684	70148	0	0
T7	35296	1006	0	0
T11	13732	114	0	0
T16	6428	64	0	0
T17	8488	148	0	0
T18	0	105940	0	0
T19	0	1162	0	0
T26	0	255794	0	0
T42	0	1432	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	1627038260	0	0
T1	13924	13688	0	0
T2	1540104	1540052	0	0
T3	87644	83452	0	0
T4	1755692	1755668	0	0
T5	1303300	1250904	0	0
T6	489684	489152	0	0
T7	35296	24444	0	0
T11	13732	10680	0	0
T16	6428	6172	0	0
T17	8488	7856	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	1627038260	0	0
T1	13924	13688	0	0
T2	1540104	1540052	0	0
T3	87644	83452	0	0
T4	1755692	1755668	0	0
T5	1303300	1250904	0	0
T6	489684	489152	0	0
T7	35296	24444	0	0
T11	13732	10680	0	0
T16	6428	6172	0	0
T17	8488	7856	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	454311833	0	0
T1	13924	3202	0	0
T2	1540104	514650	0	0
T3	87644	12120	0	0
T4	1755692	872912	0	0
T5	1303300	231958	0	0
T6	489684	70148	0	0
T7	35296	1006	0	0
T11	13732	114	0	0
T16	6428	64	0	0
T17	8488	148	0	0
T18	0	105940	0	0
T19	0	1162	0	0
T26	0	255794	0	0
T42	0	1432	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	176596399	0	0
T1	13924	514	0	0
T2	1540104	2109952	0	0
T3	87644	4426	0	0
T4	1755692	3392	0	0
T5	1303300	65304	0	0
T6	489684	108898	0	0
T7	35296	2290	0	0
T11	13732	452	0	0
T13	0	2132	0	0
T16	6428	256	0	0
T17	8488	512	0	0
T18	0	94914	0	0
T19	0	1742	0	0
T26	0	1048576	0	0
T43	0	84288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	478489498	0	0
T1	13924	3204	0	0
T2	1540104	514650	0	0
T3	87644	12120	0	0
T4	1755692	872912	0	0
T5	1303300	231958	0	0
T6	489684	80778	0	0
T7	35296	1040	0	0
T11	13732	114	0	0
T16	6428	64	0	0
T17	8488	148	0	0
T18	0	140378	0	0
T19	0	1162	0	0
T26	0	255794	0	0
T42	0	1432	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	454311833	0	0
T1	13924	3202	0	0
T2	1540104	514650	0	0
T3	87644	12120	0	0
T4	1755692	872912	0	0
T5	1303300	231958	0	0
T6	489684	70148	0	0
T7	35296	1006	0	0
T11	13732	114	0	0
T16	6428	64	0	0
T17	8488	148	0	0
T18	0	105940	0	0
T19	0	1162	0	0
T26	0	255794	0	0
T42	0	1432	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	454311833	0	0
T1	13924	3202	0	0
T2	1540104	514650	0	0
T3	87644	12120	0	0
T4	1755692	872912	0	0
T5	1303300	231958	0	0
T6	489684	70148	0	0
T7	35296	1006	0	0
T11	13732	114	0	0
T16	6428	64	0	0
T17	8488	148	0	0
T18	0	105940	0	0
T19	0	1162	0	0
T26	0	255794	0	0
T42	0	1432	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	478489498	0	0
T1	13924	3204	0	0
T2	1540104	514650	0	0
T3	87644	12120	0	0
T4	1755692	872912	0	0
T5	1303300	231958	0	0
T6	489684	80778	0	0
T7	35296	1040	0	0
T11	13732	114	0	0
T16	6428	64	0	0
T17	8488	148	0	0
T18	0	140378	0	0
T19	0	1162	0	0
T26	0	255794	0	0
T42	0	1432	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630365904	1627038260	0	0
T1	13924	13688	0	0
T2	1540104	1540052	0	0
T3	87644	83452	0	0
T4	1755692	1755668	0	0
T5	1303300	1250904	0	0
T6	489684	489152	0	0
T7	35296	24444	0	0
T11	13732	10680	0	0
T16	6428	6172	0	0
T17	8488	7856	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T18
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407591476	406759565	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	407591476	126717038	0	0
GntImpliesValid_A	407591476	126717038	0	0
GrantKnown_A	407591476	406759565	0	0
IdxKnown_A	407591476	406759565	0	0
IndexIsCorrect_A	407591476	126717038	0	0
NoReadyValidNoGrant_A	407591476	46236651	0	0
Priority_A	407591476	132883486	0	0
ReadyAndValidImplyGrant_A	407591476	126717038	0	0
ReqAndReadyImplyGrant_A	407591476	126717038	0	0
ReqImpliesValid_A	407591476	132883486	0	0
ValidKnown_A	407591476	406759565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126717038	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126717038	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126717038	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	46236651	0	0
T1	3481	189	0	0
T2	385026	530688	0	0
T3	21911	2116	0	0
T4	438923	1696	0	0
T5	325825	32652	0	0
T6	122421	32959	0	0
T7	8824	875	0	0
T11	3433	226	0	0
T16	1607	128	0	0
T17	2122	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	132883486	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	22365	0	0
T7	8824	330	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126717038	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126717038	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	132883486	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	22365	0	0
T7	8824	330	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T18
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407591476	406759565	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	407591476	126534695	0	0
GntImpliesValid_A	407591476	126534695	0	0
GrantKnown_A	407591476	406759565	0	0
IdxKnown_A	407591476	406759565	0	0
IndexIsCorrect_A	407591476	126534695	0	0
NoReadyValidNoGrant_A	407591476	46236652	0	0
Priority_A	407591476	132701142	0	0
ReadyAndValidImplyGrant_A	407591476	126534695	0	0
ReqAndReadyImplyGrant_A	407591476	126534695	0	0
ReqImpliesValid_A	407591476	132701142	0	0
ValidKnown_A	407591476	406759565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126534695	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126534695	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126534695	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	46236652	0	0
T1	3481	189	0	0
T2	385026	530688	0	0
T3	21911	2116	0	0
T4	438923	1696	0	0
T5	325825	32652	0	0
T6	122421	32959	0	0
T7	8824	875	0	0
T11	3433	226	0	0
T16	1607	128	0	0
T17	2122	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	132701142	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	22365	0	0
T7	8824	330	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126534695	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	126534695	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	19794	0	0
T7	8824	328	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	132701142	0	0
T1	3481	759	0	0
T2	385026	129428	0	0
T3	21911	3096	0	0
T4	438923	265863	0	0
T5	325825	115979	0	0
T6	122421	22365	0	0
T7	8824	330	0	0
T11	3433	57	0	0
T16	1607	32	0	0
T17	2122	74	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407591476	406759565	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	407591476	100530050	0	0
GntImpliesValid_A	407591476	100530050	0	0
GrantKnown_A	407591476	406759565	0	0
IdxKnown_A	407591476	406759565	0	0
IndexIsCorrect_A	407591476	100530050	0	0
NoReadyValidNoGrant_A	407591476	42061548	0	0
Priority_A	407591476	106452435	0	0
ReadyAndValidImplyGrant_A	407591476	100530050	0	0
ReqAndReadyImplyGrant_A	407591476	100530050	0	0
ReqImpliesValid_A	407591476	106452435	0	0
ValidKnown_A	407591476	406759565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	42061548	0	0
T1	3481	68	0	0
T2	385026	524288	0	0
T3	21911	97	0	0
T4	438923	0	0	0
T5	325825	0	0	0
T6	122421	21490	0	0
T7	8824	270	0	0
T11	3433	0	0	0
T13	0	1066	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	47457	0	0
T19	0	871	0	0
T26	0	524288	0	0
T43	0	42144	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	106452435	0	0
T1	3481	843	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	18024	0	0
T7	8824	190	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	70189	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	106452435	0	0
T1	3481	843	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	18024	0	0
T7	8824	190	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	70189	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407591476	406759565	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	407591476	100530050	0	0
GntImpliesValid_A	407591476	100530050	0	0
GrantKnown_A	407591476	406759565	0	0
IdxKnown_A	407591476	406759565	0	0
IndexIsCorrect_A	407591476	100530050	0	0
NoReadyValidNoGrant_A	407591476	42061548	0	0
Priority_A	407591476	106452435	0	0
ReadyAndValidImplyGrant_A	407591476	100530050	0	0
ReqAndReadyImplyGrant_A	407591476	100530050	0	0
ReqImpliesValid_A	407591476	106452435	0	0
ValidKnown_A	407591476	406759565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	42061548	0	0
T1	3481	68	0	0
T2	385026	524288	0	0
T3	21911	97	0	0
T4	438923	0	0	0
T5	325825	0	0	0
T6	122421	21490	0	0
T7	8824	270	0	0
T11	3433	0	0	0
T13	0	1066	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	47457	0	0
T19	0	871	0	0
T26	0	524288	0	0
T43	0	42144	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	106452435	0	0
T1	3481	843	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	18024	0	0
T7	8824	190	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	70189	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	100530050	0	0
T1	3481	842	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	15280	0	0
T7	8824	175	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	52970	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	106452435	0	0
T1	3481	843	0	0
T2	385026	127897	0	0
T3	21911	2964	0	0
T4	438923	170593	0	0
T5	325825	0	0	0
T6	122421	18024	0	0
T7	8824	190	0	0
T11	3433	0	0	0
T16	1607	0	0	0
T17	2122	0	0	0
T18	0	70189	0	0
T19	0	581	0	0
T26	0	127897	0	0
T42	0	716	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407591476	406759565	0	0
T1	3481	3422	0	0
T2	385026	385013	0	0
T3	21911	20863	0	0
T4	438923	438917	0	0
T5	325825	312726	0	0
T6	122421	122288	0	0
T7	8824	6111	0	0
T11	3433	2670	0	0
T16	1607	1543	0	0
T17	2122	1964	0	0