Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27232031	1		T1	4115		T2	14		T3	18
full_word	7937625	1		T1	17449		T2	1		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35169386	1		T1	21564		T2	15		T3	19
auto[TlIntgErrCmd]	95	1		T196	2		T251	4		T249	5
auto[TlIntgErrData]	94	1		T196	3		T251	4		T249	9
auto[TlIntgErrBoth]	81	1		T196	5		T251	2		T249	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30610962	1		T1	17957		T2	14		T3	18
auto[1]	4558694	1		T1	3607		T2	1		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26553012	1		T1	2776		T2	13		T3	17
auto[TlIntgErrNone]	partial	auto[1]	678775	1		T1	1339		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	4057826	1		T1	15181		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3879773	1		T1	2268		T4	1767		T12	53
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T196	1		T251	1		T249	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T196	1		T251	2		T249	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T279	2		T362	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T251	1		T364	1		T284	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T196	1		T251	3		T249	3
auto[TlIntgErrData]	partial	auto[1]	42	1		T196	1		T251	1		T249	4
auto[TlIntgErrData]	full_word	auto[0]	8	1		T196	1		T249	1		T358	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T249	1		T365	1		T366	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T196	1		T249	3		T357	1
auto[TlIntgErrBoth]	partial	auto[1]	37	1		T196	4		T251	2		T249	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T249	1		T366	1		T367	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T279	1		T360	2		T363	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25815	1		T195	587		T58	74		T198	1594
full_word	4472770	1		T1	16177		T4	16300		T6	13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4498338	1		T1	16177		T4	16300		T6	13
auto[TlIntgErrCmd]	69	1		T196	2		T251	1		T249	6
auto[TlIntgErrData]	107	1		T196	2		T251	6		T249	8
auto[TlIntgErrBoth]	71	1		T196	5		T251	2		T249	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4465652	1		T1	16177		T4	16300		T6	13
auto[1]	32933	1		T195	729		T58	116		T198	2084

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1607	1		T195	53		T58	1		T198	72
auto[TlIntgErrNone]	partial	auto[1]	23988	1		T195	534		T58	73		T198	1522
auto[TlIntgErrNone]	full_word	auto[0]	4463947	1		T1	16177		T4	16300		T6	13
auto[TlIntgErrNone]	full_word	auto[1]	8796	1		T195	195		T58	43		T198	562
auto[TlIntgErrCmd]	partial	auto[0]	19	1		T196	2		T249	1		T278	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T251	1		T249	4		T357	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T368	1		T366	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T249	1		T358	1		T283	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T196	1		T251	3		T249	4
auto[TlIntgErrData]	partial	auto[1]	48	1		T196	1		T251	3		T249	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T249	1		T369	1		T359	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T357	1		T360	2		T367	2
auto[TlIntgErrBoth]	partial	auto[0]	22	1		T196	1		T251	1		T249	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1		T196	4		T249	1		T357	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T363	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T251	1		T249	1		T279	1