Unified Coverage Report :: Module :: prim_prince

Module : prim_prince

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher	100.00			100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.40	100.00	86.21			100.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.40	100.00	86.21			100.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_prince

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	522	522	100.00
Total Bits 0->1	261	261	100.00
Total Bits 1->0	261	261	100.00

Ports	8	8	100.00
Port Bits	522	522	100.00
Port Bits 0->1	261	261	100.00
Port Bits 1->0	261	261	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T12	Yes	T1,T2,T3	INPUT
valid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T2,T3,T12	Yes	T12,T6,T7	INPUT
dec_i	Yes	Yes	T12,T14,T24	Yes	T12,T14,T24	INPUT
valid_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	522	522	100.00
Total Bits 0->1	261	261	100.00
Total Bits 1->0	261	261	100.00

Ports	8	8	100.00
Port Bits	522	522	100.00
Port Bits 0->1	261	261	100.00
Port Bits 1->0	261	261	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T12	Yes	T1,T2,T3	INPUT
valid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T2,T3,T12	Yes	T12,T6,T7	INPUT
dec_i	Yes	Yes	T12,T14,T24	Yes	T12,T14,T24	INPUT
valid_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	522	522	100.00
Total Bits 0->1	261	261	100.00
Total Bits 1->0	261	261	100.00

Ports	8	8	100.00
Port Bits	522	522	100.00
Port Bits 0->1	261	261	100.00
Port Bits 1->0	261	261	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T12	Yes	T1,T2,T3	INPUT
valid_i	Yes	Yes	T12,T6,T40	Yes	T12,T6,T40	INPUT
data_i[63:0]	Yes	Yes	T1,T4,T12	Yes	T1,T4,T12	INPUT
key_i[127:0]	Yes	Yes	T2,T3,T12	Yes	T12,T6,T7	INPUT
dec_i	Yes	Yes	T12,T40,T140	Yes	T12,T40,T140	INPUT
valid_o	Yes	Yes	T12,T6,T40	Yes	T12,T6,T40	OUTPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T4,T12,T6	OUTPUT