Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T33
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1649518472	1646233764	0	0
CheckNGreaterZero_A	4244	4244	0	0
GntImpliesReady_A	1649518472	462212193	0	0
GntImpliesValid_A	1649518472	462212193	0	0
GrantKnown_A	1649518472	1646233764	0	0
IdxKnown_A	1649518472	1646233764	0	0
IndexIsCorrect_A	1649518472	462212193	0	0
NoReadyValidNoGrant_A	1649518472	182430974	0	0
Priority_A	1649518472	486851831	0	0
ReadyAndValidImplyGrant_A	1649518472	462212193	0	0
ReqAndReadyImplyGrant_A	1649518472	462212193	0	0
ReqImpliesValid_A	1649518472	486851831	0	0
ValidKnown_A	1649518472	1646233764	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	1646233764	0	0
T1	331100	330444	0	0
T2	5012	4624	0	0
T3	5112	4780	0	0
T4	3077300	3076556	0	0
T5	2632952	2632684	0	0
T6	30684	30056	0	0
T7	40456	38488	0	0
T12	1601664	1601620	0	0
T19	6080	5120	0	0
T20	8656	8368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4244	4244	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T12	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	462212193	0	0
T1	331100	60312	0	0
T2	5012	64	0	0
T3	5112	64	0	0
T4	3077300	54426	0	0
T5	2632952	1139598	0	0
T6	30684	10024	0	0
T7	40456	2912	0	0
T8	0	1136	0	0
T12	1601664	514650	0	0
T19	6080	132	0	0
T20	8656	64	0	0
T22	0	1644	0	0
T33	0	28822	0	0
T47	0	732	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	462212193	0	0
T1	331100	60312	0	0
T2	5012	64	0	0
T3	5112	64	0	0
T4	3077300	54426	0	0
T5	2632952	1139598	0	0
T6	30684	10024	0	0
T7	40456	2912	0	0
T8	0	1136	0	0
T12	1601664	514650	0	0
T19	6080	132	0	0
T20	8656	64	0	0
T22	0	1644	0	0
T33	0	28822	0	0
T47	0	732	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	1646233764	0	0
T1	331100	330444	0	0
T2	5012	4624	0	0
T3	5112	4780	0	0
T4	3077300	3076556	0	0
T5	2632952	2632684	0	0
T6	30684	30056	0	0
T7	40456	38488	0	0
T12	1601664	1601620	0	0
T19	6080	5120	0	0
T20	8656	8368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	1646233764	0	0
T1	331100	330444	0	0
T2	5012	4624	0	0
T3	5112	4780	0	0
T4	3077300	3076556	0	0
T5	2632952	2632684	0	0
T6	30684	30056	0	0
T7	40456	38488	0	0
T12	1601664	1601620	0	0
T19	6080	5120	0	0
T20	8656	8368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	462212193	0	0
T1	331100	60312	0	0
T2	5012	64	0	0
T3	5112	64	0	0
T4	3077300	54426	0	0
T5	2632952	1139598	0	0
T6	30684	10024	0	0
T7	40456	2912	0	0
T8	0	1136	0	0
T12	1601664	514650	0	0
T19	6080	132	0	0
T20	8656	64	0	0
T22	0	1644	0	0
T33	0	28822	0	0
T47	0	732	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	182430974	0	0
T1	331100	86236	0	0
T2	5012	256	0	0
T3	5112	256	0	0
T4	3077300	1728408	0	0
T5	2632952	19098	0	0
T6	30684	1864	0	0
T7	40456	1796	0	0
T8	0	1708	0	0
T12	1601664	2109952	0	0
T19	6080	528	0	0
T20	8656	256	0	0
T22	0	118	0	0
T33	0	930624	0	0
T47	0	1094	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	486851831	0	0
T1	331100	71010	0	0
T2	5012	64	0	0
T3	5112	64	0	0
T4	3077300	618864	0	0
T5	2632952	1139598	0	0
T6	30684	10024	0	0
T7	40456	2912	0	0
T8	0	1136	0	0
T12	1601664	514650	0	0
T19	6080	132	0	0
T20	8656	64	0	0
T22	0	1644	0	0
T33	0	284724	0	0
T47	0	734	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	462212193	0	0
T1	331100	60312	0	0
T2	5012	64	0	0
T3	5112	64	0	0
T4	3077300	54426	0	0
T5	2632952	1139598	0	0
T6	30684	10024	0	0
T7	40456	2912	0	0
T8	0	1136	0	0
T12	1601664	514650	0	0
T19	6080	132	0	0
T20	8656	64	0	0
T22	0	1644	0	0
T33	0	28822	0	0
T47	0	732	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	462212193	0	0
T1	331100	60312	0	0
T2	5012	64	0	0
T3	5112	64	0	0
T4	3077300	54426	0	0
T5	2632952	1139598	0	0
T6	30684	10024	0	0
T7	40456	2912	0	0
T8	0	1136	0	0
T12	1601664	514650	0	0
T19	6080	132	0	0
T20	8656	64	0	0
T22	0	1644	0	0
T33	0	28822	0	0
T47	0	732	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	486851831	0	0
T1	331100	71010	0	0
T2	5012	64	0	0
T3	5112	64	0	0
T4	3077300	618864	0	0
T5	2632952	1139598	0	0
T6	30684	10024	0	0
T7	40456	2912	0	0
T8	0	1136	0	0
T12	1601664	514650	0	0
T19	6080	132	0	0
T20	8656	64	0	0
T22	0	1644	0	0
T33	0	284724	0	0
T47	0	734	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649518472	1646233764	0	0
T1	331100	330444	0	0
T2	5012	4624	0	0
T3	5112	4780	0	0
T4	3077300	3076556	0	0
T5	2632952	2632684	0	0
T6	30684	30056	0	0
T7	40456	38488	0	0
T12	1601664	1601620	0	0
T19	6080	5120	0	0
T20	8656	8368	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T33
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412379618	411558441	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	412379618	121786317	0	0
GntImpliesValid_A	412379618	121786317	0	0
GrantKnown_A	412379618	411558441	0	0
IdxKnown_A	412379618	411558441	0	0
IndexIsCorrect_A	412379618	121786317	0	0
NoReadyValidNoGrant_A	412379618	47384212	0	0
Priority_A	412379618	127992217	0	0
ReadyAndValidImplyGrant_A	412379618	121786317	0	0
ReqAndReadyImplyGrant_A	412379618	121786317	0	0
ReqImpliesValid_A	412379618	127992217	0	0
ValidKnown_A	412379618	411558441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121786317	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121786317	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121786317	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	47384212	0	0
T1	82775	21431	0	0
T2	1253	128	0	0
T3	1278	128	0	0
T4	769325	454023	0	0
T5	658238	5586	0	0
T6	7671	256	0	0
T7	10114	836	0	0
T12	400416	530688	0	0
T19	1520	264	0	0
T20	2164	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	127992217	0	0
T1	82775	16345	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	144545	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121786317	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121786317	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	127992217	0	0
T1	82775	16345	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	144545	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T33
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412379618	411558441	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	412379618	121700752	0	0
GntImpliesValid_A	412379618	121700752	0	0
GrantKnown_A	412379618	411558441	0	0
IdxKnown_A	412379618	411558441	0	0
IndexIsCorrect_A	412379618	121700752	0	0
NoReadyValidNoGrant_A	412379618	47384212	0	0
Priority_A	412379618	127906652	0	0
ReadyAndValidImplyGrant_A	412379618	121700752	0	0
ReqAndReadyImplyGrant_A	412379618	121700752	0	0
ReqImpliesValid_A	412379618	127906652	0	0
ValidKnown_A	412379618	411558441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121700752	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121700752	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121700752	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	47384212	0	0
T1	82775	21431	0	0
T2	1253	128	0	0
T3	1278	128	0	0
T4	769325	454023	0	0
T5	658238	5586	0	0
T6	7671	256	0	0
T7	10114	836	0	0
T12	400416	530688	0	0
T19	1520	264	0	0
T20	2164	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	127906652	0	0
T1	82775	16345	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	144545	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121700752	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	121700752	0	0
T1	82775	14078	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	14218	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	127906652	0	0
T1	82775	16345	0	0
T2	1253	32	0	0
T3	1278	32	0	0
T4	769325	144545	0	0
T5	658238	38094	0	0
T6	7671	4744	0	0
T7	10114	869	0	0
T12	400416	129428	0	0
T19	1520	66	0	0
T20	2164	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T33
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T12

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T33
1	1	Covered	T1,T4,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412379618	411558441	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	412379618	109362562	0	0
GntImpliesValid_A	412379618	109362562	0	0
GrantKnown_A	412379618	411558441	0	0
IdxKnown_A	412379618	411558441	0	0
IndexIsCorrect_A	412379618	109362562	0	0
NoReadyValidNoGrant_A	412379618	43831275	0	0
Priority_A	412379618	115476481	0	0
ReadyAndValidImplyGrant_A	412379618	109362562	0	0
ReqAndReadyImplyGrant_A	412379618	109362562	0	0
ReqImpliesValid_A	412379618	115476481	0	0
ValidKnown_A	412379618	411558441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	43831275	0	0
T1	82775	21687	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	410181	0	0
T5	658238	3963	0	0
T6	7671	676	0	0
T7	10114	62	0	0
T8	0	854	0	0
T12	400416	524288	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	59	0	0
T33	0	465312	0	0
T47	0	547	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	115476481	0	0
T1	82775	19160	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	164887	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	142362	0	0
T47	0	367	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	115476481	0	0
T1	82775	19160	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	164887	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	142362	0	0
T47	0	367	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T33
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T12

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T33
1	1	Covered	T1,T4,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412379618	411558441	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	412379618	109362562	0	0
GntImpliesValid_A	412379618	109362562	0	0
GrantKnown_A	412379618	411558441	0	0
IdxKnown_A	412379618	411558441	0	0
IndexIsCorrect_A	412379618	109362562	0	0
NoReadyValidNoGrant_A	412379618	43831275	0	0
Priority_A	412379618	115476481	0	0
ReadyAndValidImplyGrant_A	412379618	109362562	0	0
ReqAndReadyImplyGrant_A	412379618	109362562	0	0
ReqImpliesValid_A	412379618	115476481	0	0
ValidKnown_A	412379618	411558441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	43831275	0	0
T1	82775	21687	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	410181	0	0
T5	658238	3963	0	0
T6	7671	676	0	0
T7	10114	62	0	0
T8	0	854	0	0
T12	400416	524288	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	59	0	0
T33	0	465312	0	0
T47	0	547	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	115476481	0	0
T1	82775	19160	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	164887	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	142362	0	0
T47	0	367	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	109362562	0	0
T1	82775	16078	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	12995	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	14411	0	0
T47	0	366	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	115476481	0	0
T1	82775	19160	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	164887	0	0
T5	658238	531705	0	0
T6	7671	268	0	0
T7	10114	587	0	0
T8	0	568	0	0
T12	400416	127897	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	822	0	0
T33	0	142362	0	0
T47	0	367	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0