Unified Coverage Report :: Module Instance :: tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	82.76	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.42	100.00	89.68			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.79	100.00	78.26			88.89	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.90	100.00	78.26			93.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.42	100.00	89.68			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	26	21	80.77
Logical	26	21	80.77
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T39,T136

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T12

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T12,T6,T40
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T12

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T39,T136
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T12

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T39,T136

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T39,T136
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T4,T12

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T12

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412119811	12953459	0	0
DepthKnown_A	412119811	411298634	0	0
RvalidKnown_A	412119811	411298634	0	0
WreadyKnown_A	412119811	411298634	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412119811	12953459	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412119811	12953459	0	0
T1	82775	12651	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	11066	0	0
T5	658238	1323	0	0
T6	7671	272	0	0
T7	10114	21	0	0
T8	0	304	0	0
T12	400416	262144	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	21	0	0
T33	0	11652	0	0
T47	0	199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412119811	411298634	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412119811	411298634	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412119811	411298634	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412119811	12953459	0	0
T1	82775	12651	0	0
T2	1253	0	0	0
T3	1278	0	0	0
T4	769325	11066	0	0
T5	658238	1323	0	0
T6	7671	272	0	0
T7	10114	21	0	0
T8	0	304	0	0
T12	400416	262144	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T22	0	21	0	0
T33	0	11652	0	0
T47	0	199	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		20	20	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92		unreachable
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166		unreachable
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	23	18	78.26
Logical	23	18	78.26
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T12,T6,T40
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T12,T6,T40
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable	T12,T6,T40

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T12,T6,T40
1	1	0	Not Covered
1	1	1	Covered	T12,T6,T40

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T6,T40

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T12,T6,T40
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T12,T6,T40

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T6,T40

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Unreachable	T12,T6,T40
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412379618	11556326	0	0
DepthKnown_A	412379618	411558441	0	0
RvalidKnown_A	412379618	411558441	0	0
WreadyKnown_A	412379618	411558441	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412379618	11556326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	11556326	0	0
T5	658238	0	0	0
T6	7671	272	0	0
T7	10114	0	0	0
T8	45535	0	0	0
T12	400416	262144	0	0
T13	1148	0	0	0
T14	749	0	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T26	0	76	0	0
T32	0	24050	0	0
T40	0	26195	0	0
T55	4091	0	0	0
T65	0	11052	0	0
T117	0	262144	0	0
T133	0	124	0	0
T138	0	21768	0	0
T139	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	411558441	0	0
T1	82775	82611	0	0
T2	1253	1156	0	0
T3	1278	1195	0	0
T4	769325	769139	0	0
T5	658238	658171	0	0
T6	7671	7514	0	0
T7	10114	9622	0	0
T12	400416	400405	0	0
T19	1520	1280	0	0
T20	2164	2092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412379618	11556326	0	0
T5	658238	0	0	0
T6	7671	272	0	0
T7	10114	0	0	0
T8	45535	0	0	0
T12	400416	262144	0	0
T13	1148	0	0	0
T14	749	0	0	0
T19	1520	0	0	0
T20	2164	0	0	0
T26	0	76	0	0
T32	0	24050	0	0
T40	0	26195	0	0
T55	4091	0	0	0
T65	0	11052	0	0
T117	0	262144	0	0
T133	0	124	0	0
T138	0	21768	0	0
T139	0	16	0	0