Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22480014	1		T1	18		T2	66		T3	62
full_word	6549695	1		T2	41		T3	45		T4	162

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29029409	1		T1	18		T2	107		T3	107
auto[TlIntgErrCmd]	115	1		T195	7		T224	6		T241	11
auto[TlIntgErrData]	90	1		T195	2		T224	3		T241	4
auto[TlIntgErrBoth]	95	1		T195	1		T224	1		T241	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25034038	1		T1	17		T2	60		T3	60
auto[1]	3995671	1		T1	1		T2	47		T3	47

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21975287	1		T1	17		T2	60		T3	58
auto[TlIntgErrNone]	partial	auto[1]	504458	1		T1	1		T2	6		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	3058612	1		T3	2		T4	13		T5	125
auto[TlIntgErrNone]	full_word	auto[1]	3491052	1		T2	41		T3	43		T4	149
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T195	1		T224	2		T241	4
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T195	4		T224	4		T241	7
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T280	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T195	2		T242	1		T361	1
auto[TlIntgErrData]	partial	auto[0]	37	1		T242	1		T355	3		T280	2
auto[TlIntgErrData]	partial	auto[1]	36	1		T195	1		T224	2		T241	3
auto[TlIntgErrData]	full_word	auto[0]	11	1		T195	1		T224	1		T242	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T241	1		T355	3		T357	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T241	4		T242	2		T355	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T195	1		T224	1		T241	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T359	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T280	1		T283	1		T281	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22388	1		T64	545		T66	62		T195	8
full_word	2836911	1		T4	52		T5	4		T20	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2859017	1		T4	52		T5	4		T20	6
auto[TlIntgErrCmd]	94	1		T195	1		T224	3		T241	12
auto[TlIntgErrData]	111	1		T195	5		T224	6		T241	5
auto[TlIntgErrBoth]	77	1		T195	3		T224	1		T241	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2831715	1		T4	52		T5	4		T20	6
auto[1]	27584	1		T64	686		T66	82		T195	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1438	1		T64	35		T66	6		T223	35
auto[TlIntgErrNone]	partial	auto[1]	20693	1		T64	510		T66	56		T223	721
auto[TlIntgErrNone]	full_word	auto[0]	2830164	1		T4	52		T5	4		T20	6
auto[TlIntgErrNone]	full_word	auto[1]	6722	1		T64	176		T66	26		T223	180
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T224	1		T241	4		T280	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T195	1		T224	2		T241	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T242	1		T283	1		T284	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T241	2		T357	1		T362	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T195	3		T224	1		T241	2
auto[TlIntgErrData]	partial	auto[1]	59	1		T195	2		T224	4		T241	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T275	1		T283	1		T362	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T224	1		T355	1		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T195	1		T241	3		T242	5
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T195	1		T242	2		T355	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T224	1		T275	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T195	1		T355	1		T285	1