Unified Coverage Report :: Module :: flash_mp_data_region_sel

Module : flash_mp_data_region_sel

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_mp.u_sw_sel	100.00	100.00	100.00			100.00
tb.dut.u_flash_mp.u_hw_sel	100.00	100.00				100.00
tb.dut.u_eflash.u_region_sel	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.84			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.84			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_region_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_sw_sel

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
30	8	8
35	1	1
36	1	1
39	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE

---

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
35	1	1
36	1	1
39	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE

---

Cond Coverage for Module : flash_mp_data_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T98,T172
1	1	Covered	T32,T23,T34

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T287,T288
1	1	Covered	T32,T23,T82

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T98,T108
1	1	Covered	T32,T23,T46

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T289,T172
1	1	Covered	T23,T82,T67

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T10,T98
1	1	Covered	T5,T8,T32

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T60,T82
1	1	Covered	T5,T20,T32

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T33,T60
1	1	Covered	T5,T32,T82

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T8
1	1	Covered	T4,T5,T6

---

Branch Coverage for Module : flash_mp_data_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	51	if (region_sel[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
30	8	8
35	1	1
36	1	1
39	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T98,T172
1	1	Covered	T32,T23,T24

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T287,T288
1	1	Covered	T32,T23,T82

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T98,T108
1	1	Covered	T32,T23,T67

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T289,T172
1	1	Covered	T23,T82,T67

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T10,T98
1	1	Covered	T32,T23,T33

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T60,T82
1	1	Covered	T5,T20,T32

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T60,T91
1	1	Covered	T5,T32,T82

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T32
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	51	if (region_sel[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
35	1	1
36	1	1
39	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	51	if (region_sel[i])

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T25
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
30	8	8
35	1	1
36	1	1
39	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T290,T291
1	1	Covered	T32,T23,T34

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T288,T290,T291
1	1	Covered	T32,T23,T24

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T70,T290,T292
1	1	Covered	T23,T46,T107

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T293,T294,T290
1	1	Covered	T23,T115,T218

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T295,T220,T296
1	1	Covered	T5,T8,T32

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T218,T297,T290
1	1	Covered	T5,T32,T93

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T33,T235
1	1	Covered	T32,T125,T107

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T32
1	1	Covered	T4,T5,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	51	if (region_sel[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3