Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1630078108	1626633892	0	0
CheckNGreaterZero_A	3928	3928	0	0
GntImpliesReady_A	1630078108	450114969	0	0
GntImpliesValid_A	1630078108	450114969	0	0
GrantKnown_A	1630078108	1626633892	0	0
IdxKnown_A	1630078108	1626633892	0	0
IndexIsCorrect_A	1630078108	450114969	0	0
NoReadyValidNoGrant_A	1630078108	167289051	0	0
Priority_A	1630078108	472948908	0	0
ReadyAndValidImplyGrant_A	1630078108	450114969	0	0
ReqAndReadyImplyGrant_A	1630078108	450114969	0	0
ReqImpliesValid_A	1630078108	472948908	0	0
ValidKnown_A	1630078108	1626633892	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	1626633892	0	0
T1	4284	3916	0	0
T2	4500	3480	0	0
T3	5076	4160	0	0
T4	9256	8984	0	0
T5	13868	13264	0	0
T6	261928	261704	0	0
T7	2360	2044	0	0
T8	2272	1920	0	0
T20	6776	6136	0	0
T21	5356	4996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3928	3928	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	450114969	0	0
T1	2142	64	0	0
T2	2250	132	0	0
T3	2538	132	0	0
T4	9256	1464	0	0
T5	13868	1332	0	0
T6	261928	58320	0	0
T7	2360	118	0	0
T8	2272	116	0	0
T9	0	149920	0	0
T20	6776	854	0	0
T21	5356	64	0	0
T22	417208	43800	0	0
T23	0	9788	0	0
T32	59036	9850	0	0
T33	0	298	0	0
T48	2316	0	0	0
T49	0	1978	0	0
T81	0	14	0	0
T95	0	18168	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	450114969	0	0
T1	2142	64	0	0
T2	2250	132	0	0
T3	2538	132	0	0
T4	9256	1464	0	0
T5	13868	1332	0	0
T6	261928	58320	0	0
T7	2360	118	0	0
T8	2272	116	0	0
T9	0	149920	0	0
T20	6776	854	0	0
T21	5356	64	0	0
T22	417208	43800	0	0
T23	0	9788	0	0
T32	59036	9850	0	0
T33	0	298	0	0
T48	2316	0	0	0
T49	0	1978	0	0
T81	0	14	0	0
T95	0	18168	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	1626633892	0	0
T1	4284	3916	0	0
T2	4500	3480	0	0
T3	5076	4160	0	0
T4	9256	8984	0	0
T5	13868	13264	0	0
T6	261928	261704	0	0
T7	2360	2044	0	0
T8	2272	1920	0	0
T20	6776	6136	0	0
T21	5356	4996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	1626633892	0	0
T1	4284	3916	0	0
T2	4500	3480	0	0
T3	5076	4160	0	0
T4	9256	8984	0	0
T5	13868	13264	0	0
T6	261928	261704	0	0
T7	2360	2044	0	0
T8	2272	1920	0	0
T20	6776	6136	0	0
T21	5356	4996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	450114969	0	0
T1	2142	64	0	0
T2	2250	132	0	0
T3	2538	132	0	0
T4	9256	1464	0	0
T5	13868	1332	0	0
T6	261928	58320	0	0
T7	2360	118	0	0
T8	2272	116	0	0
T9	0	149920	0	0
T20	6776	854	0	0
T21	5356	64	0	0
T22	417208	43800	0	0
T23	0	9788	0	0
T32	59036	9850	0	0
T33	0	298	0	0
T48	2316	0	0	0
T49	0	1978	0	0
T81	0	14	0	0
T95	0	18168	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	167289051	0	0
T1	2142	256	0	0
T2	2250	528	0	0
T3	2538	528	0	0
T4	9256	392	0	0
T5	13868	950	0	0
T6	261928	2688	0	0
T7	2360	338	0	0
T8	2272	292	0	0
T9	0	80314	0	0
T20	6776	668	0	0
T21	5356	256	0	0
T22	417208	3600	0	0
T23	0	972	0	0
T32	59036	978	0	0
T33	0	754	0	0
T48	2316	0	0	0
T49	0	46	0	0
T57	0	1014	0	0
T60	0	188	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	472948908	0	0
T1	2142	64	0	0
T2	2250	132	0	0
T3	2538	132	0	0
T4	9256	1510	0	0
T5	13868	1332	0	0
T6	261928	58320	0	0
T7	2360	118	0	0
T8	2272	234	0	0
T9	0	185858	0	0
T20	6776	854	0	0
T21	5356	64	0	0
T22	417208	43800	0	0
T23	0	9788	0	0
T32	59036	9850	0	0
T33	0	298	0	0
T48	2316	0	0	0
T49	0	1978	0	0
T81	0	14	0	0
T95	0	18168	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	450114969	0	0
T1	2142	64	0	0
T2	2250	132	0	0
T3	2538	132	0	0
T4	9256	1464	0	0
T5	13868	1332	0	0
T6	261928	58320	0	0
T7	2360	118	0	0
T8	2272	116	0	0
T9	0	149920	0	0
T20	6776	854	0	0
T21	5356	64	0	0
T22	417208	43800	0	0
T23	0	9788	0	0
T32	59036	9850	0	0
T33	0	298	0	0
T48	2316	0	0	0
T49	0	1978	0	0
T81	0	14	0	0
T95	0	18168	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	450114969	0	0
T1	2142	64	0	0
T2	2250	132	0	0
T3	2538	132	0	0
T4	9256	1464	0	0
T5	13868	1332	0	0
T6	261928	58320	0	0
T7	2360	118	0	0
T8	2272	116	0	0
T9	0	149920	0	0
T20	6776	854	0	0
T21	5356	64	0	0
T22	417208	43800	0	0
T23	0	9788	0	0
T32	59036	9850	0	0
T33	0	298	0	0
T48	2316	0	0	0
T49	0	1978	0	0
T81	0	14	0	0
T95	0	18168	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	472948908	0	0
T1	2142	64	0	0
T2	2250	132	0	0
T3	2538	132	0	0
T4	9256	1510	0	0
T5	13868	1332	0	0
T6	261928	58320	0	0
T7	2360	118	0	0
T8	2272	234	0	0
T9	0	185858	0	0
T20	6776	854	0	0
T21	5356	64	0	0
T22	417208	43800	0	0
T23	0	9788	0	0
T32	59036	9850	0	0
T33	0	298	0	0
T48	2316	0	0	0
T49	0	1978	0	0
T81	0	14	0	0
T95	0	18168	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630078108	1626633892	0	0
T1	4284	3916	0	0
T2	4500	3480	0	0
T3	5076	4160	0	0
T4	9256	8984	0	0
T5	13868	13264	0	0
T6	261928	261704	0	0
T7	2360	2044	0	0
T8	2272	1920	0	0
T20	6776	6136	0	0
T21	5356	4996	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407519527	406658473	0	0
CheckNGreaterZero_A	982	982	0	0
GntImpliesReady_A	407519527	127536363	0	0
GntImpliesValid_A	407519527	127536363	0	0
GrantKnown_A	407519527	406658473	0	0
IdxKnown_A	407519527	406658473	0	0
IndexIsCorrect_A	407519527	127536363	0	0
NoReadyValidNoGrant_A	407519527	43970054	0	0
Priority_A	407519527	133421466	0	0
ReadyAndValidImplyGrant_A	407519527	127536363	0	0
ReqAndReadyImplyGrant_A	407519527	127536363	0	0
ReqImpliesValid_A	407519527	133421466	0	0
ValidKnown_A	407519527	406658473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127536363	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127536363	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127536363	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	43970054	0	0
T1	1071	128	0	0
T2	1125	264	0	0
T3	1269	264	0	0
T4	2314	177	0	0
T5	3467	475	0	0
T6	65482	1344	0	0
T7	590	169	0	0
T8	568	138	0	0
T20	1694	334	0	0
T21	1339	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	133421466	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	743	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	44	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127536363	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127536363	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	133421466	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	743	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	44	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407519527	406658473	0	0
CheckNGreaterZero_A	982	982	0	0
GntImpliesReady_A	407519527	127234042	0	0
GntImpliesValid_A	407519527	127234042	0	0
GrantKnown_A	407519527	406658473	0	0
IdxKnown_A	407519527	406658473	0	0
IndexIsCorrect_A	407519527	127234042	0	0
NoReadyValidNoGrant_A	407519527	43970055	0	0
Priority_A	407519527	133119144	0	0
ReadyAndValidImplyGrant_A	407519527	127234042	0	0
ReqAndReadyImplyGrant_A	407519527	127234042	0	0
ReqImpliesValid_A	407519527	133119144	0	0
ValidKnown_A	407519527	406658473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127234042	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127234042	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127234042	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	43970055	0	0
T1	1071	128	0	0
T2	1125	264	0	0
T3	1269	264	0	0
T4	2314	177	0	0
T5	3467	475	0	0
T6	65482	1344	0	0
T7	590	169	0	0
T8	568	138	0	0
T20	1694	334	0	0
T21	1339	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	133119144	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	743	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	44	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127234042	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	127234042	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	720	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	41	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	133119144	0	0
T1	1071	32	0	0
T2	1125	66	0	0
T3	1269	66	0	0
T4	2314	743	0	0
T5	3467	666	0	0
T6	65482	29160	0	0
T7	590	59	0	0
T8	568	44	0	0
T20	1694	427	0	0
T21	1339	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T32,T22
1	0	Covered	T4,T8,T32

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T57
1	0	Covered	T8,T32,T22
1	1	Covered	T4,T8,T32

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T32
1	1	Covered	T8,T32,T22

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T57
1	1	Covered	T4,T8,T32

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T32

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407519527	406658473	0	0
CheckNGreaterZero_A	982	982	0	0
GntImpliesReady_A	407519527	97672282	0	0
GntImpliesValid_A	407519527	97672282	0	0
GrantKnown_A	407519527	406658473	0	0
IdxKnown_A	407519527	406658473	0	0
IndexIsCorrect_A	407519527	97672282	0	0
NoReadyValidNoGrant_A	407519527	39674471	0	0
Priority_A	407519527	103204149	0	0
ReadyAndValidImplyGrant_A	407519527	97672282	0	0
ReqAndReadyImplyGrant_A	407519527	97672282	0	0
ReqImpliesValid_A	407519527	103204149	0	0
ValidKnown_A	407519527	406658473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	39674471	0	0
T4	2314	19	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	8	0	0
T9	0	40157	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	1800	0	0
T23	0	486	0	0
T32	29518	489	0	0
T33	0	377	0	0
T48	1158	0	0	0
T49	0	23	0	0
T57	0	507	0	0
T60	0	94	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	103204149	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	73	0	0
T9	0	92929	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	103204149	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	73	0	0
T9	0	92929	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T32,T22
1	0	Covered	T4,T8,T32

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T57
1	0	Covered	T8,T32,T22
1	1	Covered	T4,T8,T32

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T32
1	1	Covered	T8,T32,T22

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T57
1	1	Covered	T4,T8,T32

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T32

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407519527	406658473	0	0
CheckNGreaterZero_A	982	982	0	0
GntImpliesReady_A	407519527	97672282	0	0
GntImpliesValid_A	407519527	97672282	0	0
GrantKnown_A	407519527	406658473	0	0
IdxKnown_A	407519527	406658473	0	0
IndexIsCorrect_A	407519527	97672282	0	0
NoReadyValidNoGrant_A	407519527	39674471	0	0
Priority_A	407519527	103204149	0	0
ReadyAndValidImplyGrant_A	407519527	97672282	0	0
ReqAndReadyImplyGrant_A	407519527	97672282	0	0
ReqImpliesValid_A	407519527	103204149	0	0
ValidKnown_A	407519527	406658473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	39674471	0	0
T4	2314	19	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	8	0	0
T9	0	40157	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	1800	0	0
T23	0	486	0	0
T32	29518	489	0	0
T33	0	377	0	0
T48	1158	0	0	0
T49	0	23	0	0
T57	0	507	0	0
T60	0	94	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	103204149	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	73	0	0
T9	0	92929	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	97672282	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	17	0	0
T9	0	74960	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	103204149	0	0
T4	2314	12	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	73	0	0
T9	0	92929	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	21900	0	0
T23	0	4894	0	0
T32	29518	4925	0	0
T33	0	149	0	0
T48	1158	0	0	0
T49	0	989	0	0
T81	0	7	0	0
T95	0	9084	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0