Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25802	1		T169	642		T57	7		T172	623
full_word	2821589	1		T1	16392		T2	15937		T14	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2847108	1		T1	16392		T2	15937		T14	10
auto[TlIntgErrCmd]	80	1		T57	3		T170	4		T171	4
auto[TlIntgErrData]	99	1		T57	1		T170	7		T171	8
auto[TlIntgErrBoth]	104	1		T57	5		T170	8		T171	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2815972	1		T1	16392		T2	15937		T14	10
auto[1]	31419	1		T169	806		T57	6		T172	841

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1762	1		T169	42		T172	15		T224	9
auto[TlIntgErrNone]	partial	auto[1]	23782	1		T169	600		T172	608		T224	256
auto[TlIntgErrNone]	full_word	auto[0]	2814098	1		T1	16392		T2	15937		T14	10
auto[TlIntgErrNone]	full_word	auto[1]	7466	1		T169	206		T172	233		T224	84
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T57	1		T170	2		T171	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1		T57	2		T170	1		T171	3
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T170	1		T241	1		T274	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T57	1		T170	5		T171	3
auto[TlIntgErrData]	partial	auto[1]	47	1		T170	2		T171	4		T241	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T237	1		T281	1		T279	2
auto[TlIntgErrData]	full_word	auto[1]	5	1		T171	1		T238	1		T279	2
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T57	1		T170	2		T171	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1		T57	2		T170	5		T171	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T237	1		T369	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T57	2		T170	1		T279	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22293681	1		T1	10570		T2	11181		T3	503
full_word	6238690	1		T1	8283		T2	8647		T3	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28532071	1		T1	18853		T2	19828		T3	506
auto[TlIntgErrCmd]	86	1		T57	2		T170	5		T171	3
auto[TlIntgErrData]	92	1		T57	4		T170	7		T171	7
auto[TlIntgErrBoth]	122	1		T57	4		T170	8		T171	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24715663	1		T1	16089		T2	16992		T3	497
auto[1]	3816708	1		T1	2764		T2	2836		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21824957	1		T1	9844		T2	10411		T3	496
auto[TlIntgErrNone]	partial	auto[1]	468450	1		T1	726		T2	770		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	2890571	1		T1	6245		T2	6581		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3348093	1		T1	2038		T2	2066		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T57	2		T171	2		T241	3
auto[TlIntgErrCmd]	partial	auto[1]	41	1		T170	4		T171	1		T241	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T274	1		T281	1		T368	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T170	1		T367	1		T368	1
auto[TlIntgErrData]	partial	auto[0]	34	1		T57	2		T170	2		T171	3
auto[TlIntgErrData]	partial	auto[1]	44	1		T57	2		T170	3		T171	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T170	2		T366	2		T369	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T171	1		T277	1		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1		T57	2		T170	3		T171	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T57	2		T170	5		T171	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T366	1		T370	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T171	1		T281	1		T369	1