Unified Coverage Report :: Module :: flash_ctrl_phy_cov_if

Module : flash_ctrl_phy_cov_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	88.89			91.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if	93.52	100.00	88.89			91.67
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if	93.52	100.00	88.89			91.67

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	88.89			91.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	88.89			91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	88.89			91.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.52	100.00	88.89			91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_ctrl_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	24	1	1	100.00
CONT_ASSIGN	26	1	1	100.00
ALWAYS	32	8	8	100.00
ALWAYS	43	4	4	100.00
ALWAYS	56	3	3	100.00
CONT_ASSIGN	63	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1
26	1	1
32	1	1
33	1	1
34	2	2
35	2	2
36	2	2
			MISSING_ELSE
			MISSING_ELSE
43	1	1
44	1	1
46	1	1
47	1	1
			MISSING_ELSE
56	2	2
57	1	1
63	1	1

---

Cond Coverage for Module : flash_ctrl_phy_cov_if

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T27,T60,T61
0	0	1	0	Covered	T3,T4,T6
0	1	0	0	Covered	T4,T14,T6
1	0	0	0	Covered	T1,T2,T3

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T6
1	1	Covered	T1,T2,T3

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7
0	1	Covered	T27,T60,T61
1	0	Covered	T3,T4,T6

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_ctrl_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
IF	33	5	5	100.00
IF	43	3	3	100.00
IF	56	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if (any_vld_req)
-2-:	34	if (rd_req)
-3-:	35	if (prog_req)
-4-:	36	if ((pg_erase_req || bk_erase_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T3
1	0	1	-	Covered	T4,T14,T6
1	0	0	1	Covered	T3,T4,T6
1	0	0	0	Covered	T7
0	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	46	if (any_vld_req)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if (((!rst_ni) || (!rd_buf_en)))
-2-:	57	(any_vld_req) ? 
-3-:	57	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	24	1	1	100.00
CONT_ASSIGN	26	1	1	100.00
ALWAYS	32	8	8	100.00
ALWAYS	43	4	4	100.00
ALWAYS	56	3	3	100.00
CONT_ASSIGN	63	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1
26	1	1
32	1	1
33	1	1
34	2	2
35	2	2
36	2	2
			MISSING_ELSE
			MISSING_ELSE
43	1	1
44	1	1
46	1	1
47	1	1
			MISSING_ELSE
56	2	2
57	1	1
63	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T27,T60,T62
0	0	1	0	Covered	T3,T4,T6
0	1	0	0	Covered	T4,T6,T38
1	0	0	0	Covered	T1,T2,T3

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T38
1	1	Covered	T1,T2,T3

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7
0	1	Covered	T27,T60,T62
1	0	Covered	T3,T4,T6

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
IF	33	5	5	100.00
IF	43	3	3	100.00
IF	56	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if (any_vld_req)
-2-:	34	if (rd_req)
-3-:	35	if (prog_req)
-4-:	36	if ((pg_erase_req || bk_erase_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T3
1	0	1	-	Covered	T4,T6,T38
1	0	0	1	Covered	T3,T4,T6
1	0	0	0	Covered	T7
0	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	46	if (any_vld_req)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if (((!rst_ni) || (!rd_buf_en)))
-2-:	57	(any_vld_req) ? 
-3-:	57	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	24	1	1	100.00
CONT_ASSIGN	26	1	1	100.00
ALWAYS	32	8	8	100.00
ALWAYS	43	4	4	100.00
ALWAYS	56	3	3	100.00
CONT_ASSIGN	63	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1
26	1	1
32	1	1
33	1	1
34	2	2
35	2	2
36	2	2
			MISSING_ELSE
			MISSING_ELSE
43	1	1
44	1	1
46	1	1
47	1	1
			MISSING_ELSE
56	2	2
57	1	1
63	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Total	Covered	Percent
Conditions	27	24	88.89
Logical	27	24	88.89
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T60,T61,T62
0	0	1	0	Covered	T6,T27,T63
0	1	0	0	Covered	T14,T6,T18
1	0	0	0	Covered	T1,T2,T14

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T6,T18
1	1	Covered	T1,T2,T14

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7
0	1	Covered	T60,T61,T62
1	0	Covered	T6,T27,T63

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T14

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T14

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
IF	33	5	5	100.00
IF	43	3	3	100.00
IF	56	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if (any_vld_req)
-2-:	34	if (rd_req)
-3-:	35	if (prog_req)
-4-:	36	if ((pg_erase_req || bk_erase_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T14
1	0	1	-	Covered	T14,T6,T18
1	0	0	1	Covered	T6,T27,T63
1	0	0	0	Covered	T7
0	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	46	if (any_vld_req)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if (((!rst_ni) || (!rd_buf_en)))
-2-:	57	(any_vld_req) ? 
-3-:	57	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T14
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3