Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T14

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1665711268	1662744856	0	0
CheckNGreaterZero_A	3920	3920	0	0
GntImpliesReady_A	1665711268	447100742	0	0
GntImpliesValid_A	1665711268	447100742	0	0
GrantKnown_A	1665711268	1662744856	0	0
IdxKnown_A	1665711268	1662744856	0	0
IndexIsCorrect_A	1665711268	447100742	0	0
NoReadyValidNoGrant_A	1665711268	168104186	0	0
Priority_A	1665711268	469343616	0	0
ReadyAndValidImplyGrant_A	1665711268	447100742	0	0
ReqAndReadyImplyGrant_A	1665711268	447100742	0	0
ReqImpliesValid_A	1665711268	469343616	0	0
ValidKnown_A	1665711268	1662744856	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	1662744856	0	0
T1	193672	193296	0	0
T2	196980	196708	0	0
T3	15052	12360	0	0
T4	1693156	1629152	0	0
T5	192964	192720	0	0
T6	1500048	1499656	0	0
T14	7856	7256	0	0
T15	8820	8500	0	0
T16	6312	5644	0	0
T17	7340	6620	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3920	3920	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	447100742	0	0
T1	193672	44398	0	0
T2	196980	44160	0	0
T3	15052	376	0	0
T4	1693156	272174	0	0
T5	192964	44006	0	0
T6	1500048	241084	0	0
T10	0	456	0	0
T14	7856	898	0	0
T15	8820	64	0	0
T16	6312	132	0	0
T17	7340	134	0	0
T18	0	235378	0	0
T20	0	368	0	0
T53	0	21294	0	0
T54	0	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	447100742	0	0
T1	193672	44398	0	0
T2	196980	44160	0	0
T3	15052	376	0	0
T4	1693156	272174	0	0
T5	192964	44006	0	0
T6	1500048	241084	0	0
T10	0	456	0	0
T14	7856	898	0	0
T15	8820	64	0	0
T16	6312	132	0	0
T17	7340	134	0	0
T18	0	235378	0	0
T20	0	368	0	0
T53	0	21294	0	0
T54	0	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	1662744856	0	0
T1	193672	193296	0	0
T2	196980	196708	0	0
T3	15052	12360	0	0
T4	1693156	1629152	0	0
T5	192964	192720	0	0
T6	1500048	1499656	0	0
T14	7856	7256	0	0
T15	8820	8500	0	0
T16	6312	5644	0	0
T17	7340	6620	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	1662744856	0	0
T1	193672	193296	0	0
T2	196980	196708	0	0
T3	15052	12360	0	0
T4	1693156	1629152	0	0
T5	192964	192720	0	0
T6	1500048	1499656	0	0
T14	7856	7256	0	0
T15	8820	8500	0	0
T16	6312	5644	0	0
T17	7340	6620	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	447100742	0	0
T1	193672	44398	0	0
T2	196980	44160	0	0
T3	15052	376	0	0
T4	1693156	272174	0	0
T5	192964	44006	0	0
T6	1500048	241084	0	0
T10	0	456	0	0
T14	7856	898	0	0
T15	8820	64	0	0
T16	6312	132	0	0
T17	7340	134	0	0
T18	0	235378	0	0
T20	0	368	0	0
T53	0	21294	0	0
T54	0	36	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	168104186	0	0
T1	193672	60746	0	0
T2	196980	58310	0	0
T3	15052	1360	0	0
T4	1693156	78392	0	0
T5	192964	57084	0	0
T6	1500048	6960	0	0
T14	7856	814	0	0
T15	8820	256	0	0
T16	6312	512	0	0
T17	7340	512	0	0
T18	0	113040	0	0
T20	0	374	0	0
T36	0	26	0	0
T53	0	27392	0	0
T54	0	96	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	469343616	0	0
T1	193672	54568	0	0
T2	196980	55138	0	0
T3	15052	376	0	0
T4	1693156	272174	0	0
T5	192964	54836	0	0
T6	1500048	241084	0	0
T10	0	456	0	0
T14	7856	898	0	0
T15	8820	64	0	0
T16	6312	132	0	0
T17	7340	134	0	0
T18	0	306822	0	0
T20	0	368	0	0
T53	0	27062	0	0
T54	0	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	447100742	0	0
T1	193672	44398	0	0
T2	196980	44160	0	0
T3	15052	376	0	0
T4	1693156	272174	0	0
T5	192964	44006	0	0
T6	1500048	241084	0	0
T10	0	456	0	0
T14	7856	898	0	0
T15	8820	64	0	0
T16	6312	132	0	0
T17	7340	134	0	0
T18	0	235378	0	0
T20	0	368	0	0
T53	0	21294	0	0
T54	0	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	447100742	0	0
T1	193672	44398	0	0
T2	196980	44160	0	0
T3	15052	376	0	0
T4	1693156	272174	0	0
T5	192964	44006	0	0
T6	1500048	241084	0	0
T10	0	456	0	0
T14	7856	898	0	0
T15	8820	64	0	0
T16	6312	132	0	0
T17	7340	134	0	0
T18	0	235378	0	0
T20	0	368	0	0
T53	0	21294	0	0
T54	0	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	469343616	0	0
T1	193672	54568	0	0
T2	196980	55138	0	0
T3	15052	376	0	0
T4	1693156	272174	0	0
T5	192964	54836	0	0
T6	1500048	241084	0	0
T10	0	456	0	0
T14	7856	898	0	0
T15	8820	64	0	0
T16	6312	132	0	0
T17	7340	134	0	0
T18	0	306822	0	0
T20	0	368	0	0
T53	0	27062	0	0
T54	0	36	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1665711268	1662744856	0	0
T1	193672	193296	0	0
T2	196980	196708	0	0
T3	15052	12360	0	0
T4	1693156	1629152	0	0
T5	192964	192720	0	0
T6	1500048	1499656	0	0
T14	7856	7256	0	0
T15	8820	8500	0	0
T16	6312	5644	0	0
T17	7340	6620	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416427817	415686214	0	0
CheckNGreaterZero_A	980	980	0	0
GntImpliesReady_A	416427817	116995616	0	0
GntImpliesValid_A	416427817	116995616	0	0
GrantKnown_A	416427817	415686214	0	0
IdxKnown_A	416427817	415686214	0	0
IndexIsCorrect_A	416427817	116995616	0	0
NoReadyValidNoGrant_A	416427817	43634663	0	0
Priority_A	416427817	122552770	0	0
ReadyAndValidImplyGrant_A	416427817	116995616	0	0
ReqAndReadyImplyGrant_A	416427817	116995616	0	0
ReqImpliesValid_A	416427817	122552770	0	0
ValidKnown_A	416427817	415686214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116995616	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116995616	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116995616	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	43634663	0	0
T1	48418	15920	0	0
T2	49245	15321	0	0
T3	3763	680	0	0
T4	423289	39196	0	0
T5	48241	14446	0	0
T6	375012	3289	0	0
T14	1964	256	0	0
T15	2205	128	0	0
T16	1578	256	0	0
T17	1835	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	122552770	0	0
T1	48418	14774	0	0
T2	49245	13976	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	14854	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116995616	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116995616	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	122552770	0	0
T1	48418	14774	0	0
T2	49245	13976	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	14854	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416427817	415686214	0	0
CheckNGreaterZero_A	980	980	0	0
GntImpliesReady_A	416427817	116800322	0	0
GntImpliesValid_A	416427817	116800322	0	0
GrantKnown_A	416427817	415686214	0	0
IdxKnown_A	416427817	415686214	0	0
IndexIsCorrect_A	416427817	116800322	0	0
NoReadyValidNoGrant_A	416427817	43634663	0	0
Priority_A	416427817	122357476	0	0
ReadyAndValidImplyGrant_A	416427817	116800322	0	0
ReqAndReadyImplyGrant_A	416427817	116800322	0	0
ReqImpliesValid_A	416427817	122357476	0	0
ValidKnown_A	416427817	415686214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116800322	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116800322	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116800322	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	43634663	0	0
T1	48418	15920	0	0
T2	49245	15321	0	0
T3	3763	680	0	0
T4	423289	39196	0	0
T5	48241	14446	0	0
T6	375012	3289	0	0
T14	1964	256	0	0
T15	2205	128	0	0
T16	1578	256	0	0
T17	1835	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	122357476	0	0
T1	48418	14774	0	0
T2	49245	13976	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	14854	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116800322	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	116800322	0	0
T1	48418	11869	0	0
T2	49245	11379	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	11554	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	122357476	0	0
T1	48418	14774	0	0
T2	49245	13976	0	0
T3	3763	188	0	0
T4	423289	136087	0	0
T5	48241	14854	0	0
T6	375012	42501	0	0
T14	1964	64	0	0
T15	2205	32	0	0
T16	1578	66	0	0
T17	1835	67	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416427817	415686214	0	0
CheckNGreaterZero_A	980	980	0	0
GntImpliesReady_A	416427817	106652402	0	0
GntImpliesValid_A	416427817	106652402	0	0
GrantKnown_A	416427817	415686214	0	0
IdxKnown_A	416427817	415686214	0	0
IndexIsCorrect_A	416427817	106652402	0	0
NoReadyValidNoGrant_A	416427817	40417430	0	0
Priority_A	416427817	112216685	0	0
ReadyAndValidImplyGrant_A	416427817	106652402	0	0
ReqAndReadyImplyGrant_A	416427817	106652402	0	0
ReqImpliesValid_A	416427817	112216685	0	0
ValidKnown_A	416427817	415686214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	40417430	0	0
T1	48418	14453	0	0
T2	49245	13834	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	14096	0	0
T6	375012	191	0	0
T14	1964	151	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	56520	0	0
T20	0	187	0	0
T36	0	13	0	0
T53	0	13696	0	0
T54	0	48	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	112216685	0	0
T1	48418	12510	0	0
T2	49245	13593	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	12564	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	153411	0	0
T20	0	184	0	0
T53	0	13531	0	0
T54	0	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	112216685	0	0
T1	48418	12510	0	0
T2	49245	13593	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	12564	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	153411	0	0
T20	0	184	0	0
T53	0	13531	0	0
T54	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416427817	415686214	0	0
CheckNGreaterZero_A	980	980	0	0
GntImpliesReady_A	416427817	106652402	0	0
GntImpliesValid_A	416427817	106652402	0	0
GrantKnown_A	416427817	415686214	0	0
IdxKnown_A	416427817	415686214	0	0
IndexIsCorrect_A	416427817	106652402	0	0
NoReadyValidNoGrant_A	416427817	40417430	0	0
Priority_A	416427817	112216685	0	0
ReadyAndValidImplyGrant_A	416427817	106652402	0	0
ReqAndReadyImplyGrant_A	416427817	106652402	0	0
ReqImpliesValid_A	416427817	112216685	0	0
ValidKnown_A	416427817	415686214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	40417430	0	0
T1	48418	14453	0	0
T2	49245	13834	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	14096	0	0
T6	375012	191	0	0
T14	1964	151	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	56520	0	0
T20	0	187	0	0
T36	0	13	0	0
T53	0	13696	0	0
T54	0	48	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	112216685	0	0
T1	48418	12510	0	0
T2	49245	13593	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	12564	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	153411	0	0
T20	0	184	0	0
T53	0	13531	0	0
T54	0	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	106652402	0	0
T1	48418	10330	0	0
T2	49245	10701	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	10449	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	117689	0	0
T20	0	184	0	0
T53	0	10647	0	0
T54	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	112216685	0	0
T1	48418	12510	0	0
T2	49245	13593	0	0
T3	3763	0	0	0
T4	423289	0	0	0
T5	48241	12564	0	0
T6	375012	78041	0	0
T10	0	228	0	0
T14	1964	385	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	153411	0	0
T20	0	184	0	0
T53	0	13531	0	0
T54	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0