Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.28		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T228,T229,T8
1	0	Covered	T228,T229,T8

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T6
1	1	Covered	T228,T229,T8

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T228,T229,T8
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T14,T6
1	Covered	T14,T6,T17

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T6
1	0	Covered	T4,T14,T6
1	1	Covered	T4,T14,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T6
1	1	Covered	T6,T18,T56

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T7
1	Covered	T6,T18,T56

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T6
1	0	Covered	T4,T14,T6
1	1	Covered	T4,T14,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T14,T6
1	Covered	T4,T14,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T18
1	0	Covered	T4,T14,T6
1	1	Covered	T14,T6,T17

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T7
1	Covered	T14,T6,T17

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T14,T20

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T14,T6
1	Covered	T4,T14,T6

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T14,T6,T38
1	Covered	T4,T14,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T6
1	1	Covered	T4,T14,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T20
1	1	Covered	T4,T14,T20

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T14,T20
1	1	Covered	T4,T14,T20

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T14,T6
1	1	0	Covered	T4,T14,T6
1	1	1	Covered	T4,T14,T6

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T6

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T14,T20
StCalcMask	237	Covered	T4,T14,T20
StCalcPlainEcc	215	Covered	T4,T14,T6
StDisabled	193	Covered	T3,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T14,T6
StPostPack	218	Covered	T14,T6,T17
StPrePack	195	Covered	T6,T18,T56
StReqFlash	237	Covered	T4,T14,T6
StScrambleData	244	Covered	T4,T14,T20
StWaitFlash	270	Covered	T4,T14,T6

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T14,T20
StCalcMask->StScrambleData	244	Covered	T4,T14,T20
StCalcPlainEcc->StCalcMask	237	Covered	T4,T14,T20
StCalcPlainEcc->StReqFlash	237	Covered	T6,T38,T18
StIdle->StDisabled	193	Covered	T3,T10,T11
StIdle->StPackData	197	Covered	T4,T14,T6
StIdle->StPrePack	195	Covered	T6,T18,T56
StPackData->StCalcPlainEcc	215	Covered	T4,T14,T6
StPackData->StPostPack	218	Covered	T14,T6,T17
StPostPack->StCalcPlainEcc	231	Covered	T14,T6,T38
StPrePack->StPackData	205	Covered	T6,T18,T56
StReqFlash->StIdle	273	Covered	T4,T14,T6
StReqFlash->StWaitFlash	270	Covered	T4,T14,T6
StScrambleData->StCalcEcc	252	Covered	T4,T14,T20
StWaitFlash->StIdle	280	Covered	T4,T14,T6

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T14,T6
0	0	1	Covered	T4,T14,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T56
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T14,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T56
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T7
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T14,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T6,T17
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T14,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T14,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T14,T6,T17
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T14,T20
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T38,T18
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T14,T20
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T14,T20
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T14,T20
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T14,T20
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T14,T20
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T14,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T14,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T14,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T14,T6,T38
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T14,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T14,T6
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T7

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T14,T6
0	0	1	-	-	Covered	T4,T14,T20
0	0	0	1	-	Covered	T4,T14,T20
0	0	0	0	1	Covered	T4,T14,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T14,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	832855634	2377771	0	0
PostPackRule_A	832855634	22072	0	0
PrePackRule_A	832855634	11150	0	0
WidthCheck_A	1960	1960	0	0
u_state_regs_A	832855634	831372428	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832855634	2377771	0	0
T4	423289	312	0	0
T5	96482	0	0	0
T6	750024	305	0	0
T10	0	1	0	0
T14	3928	1	0	0
T15	4410	0	0	0
T16	3156	0	0	0
T17	3670	0	0	0
T18	860810	1517	0	0
T20	2925	1	0	0
T26	0	32	0	0
T27	0	401	0	0
T32	3068	0	0	0
T36	0	1	0	0
T37	0	32	0	0
T38	3852	0	0	0
T42	0	71	0	0
T56	0	2	0	0
T60	0	181	0	0
T61	0	3	0	0
T63	0	65920	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832855634	22072	0	0
T5	48241	0	0	0
T6	750024	9	0	0
T10	1059	0	0	0
T14	1964	1	0	0
T15	4410	0	0	0
T16	3156	0	0	0
T17	3670	0	0	0
T18	860810	578	0	0
T20	5850	1	0	0
T27	0	11	0	0
T32	3068	0	0	0
T36	0	1	0	0
T38	3852	1	0	0
T56	0	2	0	0
T60	0	15	0	0
T61	0	4	0	0
T62	0	3	0	0
T78	0	9	0	0
T91	2112	0	0	0
T107	0	34	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832855634	11150	0	0
T6	750024	8	0	0
T10	2118	0	0	0
T15	4410	0	0	0
T16	3156	0	0	0
T17	3670	0	0	0
T18	860810	259	0	0
T19	0	222	0	0
T20	5850	0	0	0
T27	0	9	0	0
T32	3068	0	0	0
T38	3852	0	0	0
T56	0	1	0	0
T60	0	11	0	0
T61	0	3	0	0
T62	0	3	0	0
T78	0	18	0	0
T79	0	6	0	0
T91	4224	0	0	0
T107	0	32	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1960	1960	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832855634	831372428	0	0
T1	96836	96648	0	0
T2	98490	98354	0	0
T3	7526	6180	0	0
T4	846578	814576	0	0
T5	96482	96360	0	0
T6	750024	749828	0	0
T14	3928	3628	0	0
T15	4410	4250	0	0
T16	3156	2822	0	0
T17	3670	3310	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T16

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T16

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T228,T229,T8
1	0	Covered	T228,T229,T8

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16
1	1	Covered	T228,T229,T8

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T228,T229,T8
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T17

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T6,T38
1	Covered	T6,T17,T38

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T38
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T6,T38

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T38

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16
1	1	Covered	T6,T18,T56

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T7
1	Covered	T6,T18,T56

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T38
1	0	Covered	T4,T6,T16
1	1	Covered	T4,T6,T38

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T6,T16
1	Covered	T4,T6,T38

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T18
1	0	Covered	T4,T6,T16
1	1	Covered	T6,T17,T38

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T7
1	Covered	T6,T17,T38

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T42,T86

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T38
1	Covered	T4,T6,T38

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T6,T38

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T38
1	1	Covered	T4,T6,T38

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T42,T86
1	1	Covered	T4,T42,T86

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T42,T86
1	1	Covered	T4,T42,T86

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T17
1	1	0	Covered	T4,T6,T16
1	1	1	Covered	T4,T6,T18

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T18

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T42,T86
StCalcMask	237	Covered	T4,T42,T86
StCalcPlainEcc	215	Covered	T4,T6,T38
StDisabled	193	Covered	T3,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T6,T16
StPostPack	218	Covered	T6,T17,T38
StPrePack	195	Covered	T6,T18,T56
StReqFlash	237	Covered	T4,T6,T38
StScrambleData	244	Covered	T4,T42,T86
StWaitFlash	270	Covered	T4,T6,T38

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T42,T86
StCalcMask->StScrambleData	244	Covered	T4,T42,T86
StCalcPlainEcc->StCalcMask	237	Covered	T4,T42,T86
StCalcPlainEcc->StReqFlash	237	Covered	T6,T38,T18
StIdle->StDisabled	193	Covered	T3,T10,T11
StIdle->StPackData	197	Covered	T4,T6,T16
StIdle->StPrePack	195	Covered	T6,T18,T56
StPackData->StCalcPlainEcc	215	Covered	T4,T6,T38
StPackData->StPostPack	218	Covered	T6,T17,T38
StPostPack->StCalcPlainEcc	231	Covered	T6,T38,T18
StPrePack->StPackData	205	Covered	T6,T18,T56
StReqFlash->StIdle	273	Covered	T4,T6,T38
StReqFlash->StWaitFlash	270	Covered	T4,T6,T38
StScrambleData->StCalcEcc	252	Covered	T4,T42,T86
StWaitFlash->StIdle	280	Covered	T4,T6,T38

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T38
0	0	1	Covered	T4,T6,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T56
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T16
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T56
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T7
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T38
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T17,T38
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T6,T16
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T6,T38
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T6,T17,T38
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T42,T86
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T38,T18
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T42,T86
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T42,T86
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T42,T86
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T42,T86
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T42,T86
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T6,T38
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T6,T38
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T6,T38
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T6,T38,T18
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T18
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T38
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T7

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T6,T38
0	0	1	-	-	Covered	T4,T42,T86
0	0	0	1	-	Covered	T4,T42,T86
0	0	0	0	1	Covered	T4,T6,T17
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T38
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	416427817	1202414	0	0
PostPackRule_A	416427817	12771	0	0
PrePackRule_A	416427817	6625	0	0
WidthCheck_A	980	980	0	0
u_state_regs_A	416427817	415686214	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	1202414	0	0
T4	423289	312	0	0
T5	48241	0	0	0
T6	375012	101	0	0
T14	1964	0	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	430405	918	0	0
T26	0	32	0	0
T27	0	167	0	0
T32	1534	0	0	0
T37	0	32	0	0
T38	1926	0	0	0
T42	0	71	0	0
T56	0	2	0	0
T60	0	169	0	0
T63	0	33152	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	12771	0	0
T6	375012	1	0	0
T10	1059	0	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	430405	342	0	0
T20	2925	0	0	0
T27	0	6	0	0
T32	1534	0	0	0
T38	1926	1	0	0
T56	0	2	0	0
T60	0	5	0	0
T61	0	2	0	0
T62	0	1	0	0
T78	0	9	0	0
T91	2112	0	0	0
T107	0	13	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	6625	0	0
T6	375012	2	0	0
T10	1059	0	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	430405	189	0	0
T19	0	169	0	0
T20	2925	0	0	0
T27	0	4	0	0
T32	1534	0	0	0
T38	1926	0	0	0
T56	0	1	0	0
T60	0	5	0	0
T61	0	2	0	0
T62	0	1	0	0
T78	0	9	0	0
T91	2112	0	0	0
T107	0	13	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T6,T18

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T6,T18

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T230
1	0	Covered	T8,T9,T230

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T6,T18
1	1	Covered	T8,T9,T230

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T230
1	0	Covered	T1,T2,T14

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T6,T18

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T14,T6,T18
1	Covered	T14,T6,T18

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T18
1	0	Covered	T14,T6,T18
1	1	Covered	T14,T6,T18

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T6,T18

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T6,T18
1	1	Covered	T6,T18,T27

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T7
1	Covered	T6,T18,T27

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T18
1	0	Covered	T14,T6,T18
1	1	Covered	T14,T6,T18

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T14,T6,T18
1	Covered	T14,T6,T18

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T10
1	0	Covered	T14,T6,T18
1	1	Covered	T14,T6,T18

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T7
1	Covered	T14,T6,T18

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T6,T18,T36
1	Covered	T14,T20,T10

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T14,T6,T18
1	Covered	T14,T6,T18

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T14,T6,T18
1	Covered	T14,T6,T18

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T6,T18
1	1	Covered	T14,T6,T18

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T20,T54
1	0	Covered	T14,T20,T10
1	1	Covered	T14,T20,T10

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T20,T54
1	0	Covered	T14,T20,T10
1	1	Covered	T14,T20,T10

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T6,T18
1	1	0	Covered	T14,T6,T18
1	1	1	Covered	T14,T6,T18

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T6,T18

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T14

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T14,T20,T10
StCalcMask	237	Covered	T14,T20,T10
StCalcPlainEcc	215	Covered	T14,T6,T18
StDisabled	193	Covered	T3,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T14,T6,T18
StPostPack	218	Covered	T14,T6,T18
StPrePack	195	Covered	T6,T18,T27
StReqFlash	237	Covered	T14,T6,T18
StScrambleData	244	Covered	T14,T20,T10
StWaitFlash	270	Covered	T14,T6,T18

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T14,T20,T10
StCalcMask->StScrambleData	244	Covered	T14,T20,T10
StCalcPlainEcc->StCalcMask	237	Covered	T14,T20,T10
StCalcPlainEcc->StReqFlash	237	Covered	T6,T18,T36
StIdle->StDisabled	193	Covered	T3,T10,T11
StIdle->StPackData	197	Covered	T14,T6,T18
StIdle->StPrePack	195	Covered	T6,T18,T27
StPackData->StCalcPlainEcc	215	Covered	T14,T6,T18
StPackData->StPostPack	218	Covered	T14,T6,T18
StPostPack->StCalcPlainEcc	231	Covered	T14,T6,T18
StPrePack->StPackData	205	Covered	T6,T18,T27
StReqFlash->StIdle	273	Covered	T14,T6,T18
StReqFlash->StWaitFlash	270	Covered	T14,T6,T18
StScrambleData->StCalcEcc	252	Covered	T14,T20,T10
StWaitFlash->StIdle	280	Covered	T14,T6,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T6,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T6,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T6,T18
0	1	Covered	T1,T2,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T14,T6,T18
0	0	1	Covered	T14,T6,T18
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T27
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T6,T18
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T18,T27
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T7
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T6,T18
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T6,T18
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T14,T6,T18
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T14,T6,T18
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T14,T6,T18
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T20,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T18,T36
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T14,T20,T10
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T14,T20,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T20,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T14,T20,T10
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T20,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T14,T6,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T14,T6,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T14,T6,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T14,T6,T18
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T6,T18
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T14,T6,T18
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T7

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T14,T6,T18
0	0	1	-	-	Covered	T14,T20,T10
0	0	0	1	-	Covered	T14,T20,T10
0	0	0	0	1	Covered	T14,T6,T18
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T14,T6,T18
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	416427817	1175357	0	0
PostPackRule_A	416427817	9301	0	0
PrePackRule_A	416427817	4525	0	0
WidthCheck_A	980	980	0	0
u_state_regs_A	416427817	415686214	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	1175357	0	0
T5	48241	0	0	0
T6	375012	204	0	0
T10	0	1	0	0
T14	1964	1	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	430405	599	0	0
T20	2925	1	0	0
T27	0	234	0	0
T32	1534	0	0	0
T36	0	1	0	0
T38	1926	0	0	0
T60	0	12	0	0
T61	0	3	0	0
T63	0	32768	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	9301	0	0
T5	48241	0	0	0
T6	375012	8	0	0
T14	1964	1	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	430405	236	0	0
T20	2925	1	0	0
T27	0	5	0	0
T32	1534	0	0	0
T36	0	1	0	0
T38	1926	0	0	0
T60	0	10	0	0
T61	0	2	0	0
T62	0	2	0	0
T107	0	21	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	4525	0	0
T6	375012	6	0	0
T10	1059	0	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	430405	70	0	0
T19	0	53	0	0
T20	2925	0	0	0
T27	0	5	0	0
T32	1534	0	0	0
T38	1926	0	0	0
T60	0	6	0	0
T61	0	1	0	0
T62	0	2	0	0
T78	0	9	0	0
T79	0	6	0	0
T91	2112	0	0	0
T107	0	19	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	980	980	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416427817	415686214	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0